Datasheet

Analog-to-Digital Converter (ADC)
MC68HC908QY/QT Family Data Sheet, Rev. 6
46 Freescale Semiconductor
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is
cleared when ADR is read or ADSCR is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update ADR at the end of each conversion.
Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
CH[4:0] — ADC Channel Select Bits
CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of the four ADC channels.
The five select bits are detailed in Table 3-1. Care should be taken when using a port pin as both an
analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to 1.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 3-1. MUX Channel Select
CH4 CH3 CH2 CH1 CH0
ADC
Channel
Input Select
00000 ADC0 PTA0
00001 ADC1 PTA1
00010 ADC2 PTA4
00011 ADC3 PTA5
00100 —
Unused
(1)
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
↓↓↓↓↓ —
11010 —
11011 — Reserved
11
1 0 0 — Unused
11
1 0 1—
V
DDA
(2)
2. The voltage levels supplied from internal reference nodes, as specified in the
table, are used to verify the operation of the ADC converter both in produc-
tion test and for user applications.
11
1 1 0—
V
SSA
(2)
111 1 1—ADC power off