Datasheet

FLASH Memory (FLASH)
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor 37
Figure 2-4. FLASH Programming Flowchart
SET HVEN BIT
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
WAIT FOR A TIME, t
NVS
SET PGM BIT
WAIT FOR A TIME, t
PGS
WRITE DATA TO THE FLASH ADDRESS
TO BE PROGRAMMED
WAIT FOR A TIME, t
PROG
CLEAR PGM BIT
WAIT FOR A TIME, t
NVH
CLEAR HVEN BIT
WAIT FOR A TIME, t
RCV
COMPLETED
PROGRAMMING
THIS ROW?
Y
N
END OF PROGRAMMING
The time between each FLASH address change (step 7 to step 7),
must not exceed the maximum programming
time, t
PROG
max.
or the time between the last FLASH address programmed
to clearing PGM bit (step 7 to step 10)
NOTES:
1
3
4
5
6
7
8
10
11
12
13
Algorithm for Programming
a Row (32 Bytes) of FLASH Memory
This row program algorithm assumes the row/s
to be programmed are initially erased.
9
READ THE FLASH BLOCK PROTECT REGISTER
2