Datasheet

Memory
MC68HC908QY/QT Family Data Sheet, Rev. 6
30 Freescale Semiconductor
$0039
↓
$003B
Unimplemented
$003C
ADC Status and Control
Register (ADSCR)
See page 45.
Read: COCO
AIEN ADCO CH4 CH3 CH2 CH1 CH0
Write: R
Reset:00011111
$003D Unimplemented
$003E
ADC Data Register
(ADR)
See page 47.
Read:
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Indeterminate after reset
$003F
ADC Input Clock Register
(ADICLK)
See page 47.
Read:
ADIV2 ADIV1 ADIV0
00000
Write:
Reset:00000000
$FE00
Break Status Register
(BSR)
See page 137.
Read:
RRRRRR
SBSW
R
Write: See note 1
Reset: 0
1. Writing a 0 clears SBSW.
$FE01
SIM Reset Status Register
(SRSR)
See page 117.
Read: POR PIN COP ILOP ILAD MODRST LVI 0
Write:
POR:10000000
$FE02
Break Auxiliary
Register (BRKAR)
See page 137.
Read:0000000
BDCOP
Write:
Reset:00000000
$FE03
Break Flag Control
Register (BFCR)
See page 138.
Read:
BCFERRRRRRR
Write:
Reset: 0
$FE04
Interrupt Status Register 1
(INT1)
See page 77.
Read: 0 IF5 IF4 IF3 0 IF1 0 0
Write:RRRRRRRR
Reset:00000000
$FE05
Interrupt Status Register 2
(INT2)
See page 77.
Read:IF140000000
Write:RRRRRRRR
Reset:00000000
$FE06
Interrupt Status Register 3
(INT3)
See page 77.
Read:0000000IF15
Write:RRRRRRRR
Reset:00000000
$FE07 Reserved RRRRRRRR
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)