Datasheet

Input/Output (I/O) Section
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor 27
2.4 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have these addresses:
• $FE00 — Break status register, BSR
• $FE01 — Reset status register, SRSR
• $FE02 — Break auxiliary register, BRKAR
• $FE03 — Break flag control register, BFCR
• $FE04 — Interrupt status register 1, INT1
• $FE05 — Interrupt status register 2, INT2
• $FE06 — Interrupt status register 3, INT3
•$FE07 — Reserved
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
•$FE0D — Reserved
• $FFBE — FLASH block protect register, FLBPR
• $FFC0 — Internal OSC trim value (factory programmed, VDD = 5.0 V)
• $FFC1 — Internal OSC trim value (factory programmed, VDD = 3.0 V)
• $FFFF — COP control register, COPCTL
Addr.Register Name Bit 7654321Bit 0
$0000
Port A Data Register
(PTA)
See page 98.
Read:
R
AWUL
PTA5 PTA4 PTA3
PTA2
PTA1 PTA0
Write:
Reset: Unaffected by reset
$0001
Port B Data Register
(PTB)
See page 100.
Read:
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
Write:
Reset: Unaffected by reset
$0002 Unimplemented
$0003 Unimplemented
$0004
Data Direction Register A
(DDRA)
See page 98.
Read:
R R DDRA5 DDRA4 DDRA3
0
DDRA1 DDRA0
Write:
Reset:00000000
$0005
Data Direction Register B
(DDRB)
See page 101.
Read:
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)