Datasheet

5-V Control Timing
MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor 153
16.7 5-V Control Timing
Figure 16-3. RST and IRQ Timing
Characteristic
(1)
1. V
DD
= 4.5 to 5.5 Vdc, V
SS
= 0 Vdc, T
A
= T
L
to T
H
; timing shown with respect to 20% V
DD
and 70% V
SS
, unless otherwise
noted.
Symbol Min Max Unit
Internal operating frequency
f
OP
(f
Bus
)
—8MHz
Internal clock period (1/f
OP
)t
cyc
125 — ns
RST
input pulse width low
t
RL
100 — ns
IRQ
interrupt pulse width low (edge-triggered)
t
ILIH
100 — ns
IRQ
interrupt pulse period
t
ILIL
Note
(2)
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 t
cyc
.
—
t
cyc
RST
IRQ
t
RL
t
ILIH
t
ILIL