Datasheet

Break Module (BRK)

MC68HC908QY/QT Family Data Sheet, Rev. 6

Freescale Semiconductor 137

15.2.2.3 Break Auxiliary Register

The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the

MCU is in a state of break interrupt with monitor mode.

BDCOP — Break Disable COP Bit

This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.

1 = COP disabled during break interrupt

0 = COP enabled during break interrupt

15.2.2.4 Break Status Register

The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.

This register is only used in emulation mode.

SBSW — SIM Break Stop/Wait

SBSW can be read within the break state SWI routine. The user can modify the return address on the

stack by subtracting one from it.

1 = Wait mode was exited by break interrupt

0 = Wait mode was not exited by break interrupt

Address:

$FE02

Bit 7654321Bit 0

BDCOP

Write:

Reset:00000000

= Unimplemented

Figure 15-6. Break Auxiliary Register (BRKAR)

Address: $FE00

Bit 7654321Bit 0

Read:

RRRRRR

SBSW

Write: Note

(1)

Reset: 0

R = Reserved 1. Writing a 0 clears SBSW.

Figure 15-7. Break Status Register (BSR)