Datasheet

MC68HC908QY/QT Family Data Sheet, Rev. 6
Freescale Semiconductor 103
Chapter 13
System Integration Module (SIM)
13.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or
internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit
(MCU) activities. A block diagram of the SIM is shown in Figure 13-1. The SIM is a system state controller
that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
Table 13-1. Signal Name Conventions
Signal Name Description
BUSCLKX4 Buffered clock from the internal, RC or XTAL oscillator circuit.
BUSCLKX2
The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to
generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4).
Address bus Internal address bus
Data bus Internal data bus
PORRST Signal from the power-on reset module to the SIM
IRST Internal reset signal
R/W
Read/write signal