Datasheet

Break Module (BRK)

Break Module Registers

MC68HC908GR8 — Rev 4.0 Technical Data

MOTOROLA Break Module (BRK) 97

BW — Break Wait Bit

This read/write bit is set when a break interrupt causes an exit from

wait mode. Clear BW by writing a logic 0 to it. Reset clears BW.

1 = Break interrupt during wait mode

0 = No break interrupt during wait mode

BW can be read within the break interrupt routine. The user can modify

the return address on the stack by subtracting 1 from it. The following

code is an example.

This code works if the H register was stacked in the break interrupt

routine. Execute this code at the end of the break interrupt routine.

HIBYTE EQU 5

LOBYTE EQU 6

; If not BW, do RTI

BRCLR BW,BSR, RETURN ;

;

See if wait mode or stop mode

was exited by break.

TST LOBYTE,SP ; If RETURNLO is not 0,

BNE DOLO ; then just decrement low byte.

DEC HIBYTE,SP ; Else deal with high byte also.

DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode.

RETURN PULH

RTI

; Restore H register.

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

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