Datasheet

Resets and Interrupts
Interrupts
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Resets and Interrupts 71
4.4.2.1 SWI Instruction
The software interrupt instruction (SWI) causes a non-maskable
interrupt.
NOTE: A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
4.4.2.2 Break Interrupt
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
4.4.2.3 IRQ Pin
A logic 0 on the IRQ1 pin latches an external interrupt request.
4.4.2.4 CGM
The CGM can generate a CPU interrupt request every time the phase-
locked loop circuit (PLL) enters or leaves the locked state. When the
LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.
4.4.2.5 TIM1
TIM1 CPU interrupt sources:
• TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1
counter value rolls over to $0000 after matching the value in the
TIM1 counter modulo registers. The TIM1 overflow interrupt
enable bit, TOIE, enables TIM1 overflow CPU interrupt requests.
TOF and TOIE are in the TIM1 status and control register.
• TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. The channel
x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x
status and control register.
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cale Semiconductor,
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