Datasheet

Resets and Interrupts
Technical Data MC68HC908GR8 — Rev 4.0
66 Resets and Interrupts MOTOROLA
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
LVI — Low-Voltage Inhibit Reset Bit
1 = Last reset caused by low-power supply voltage
0 = POR or read of SRSR
4.4 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. An interrupt does not stop the operation of
the instruction being executed, but begins when the current instruction
completes its operation.
4.4.1 Effects
An interrupt:
• Saves the CPU registers on the stack. At the end of the interrupt,
the RTI instruction recovers the CPU registers from the stack so
that normal processing can resume.
• Sets the interrupt mask (I bit) to prevent additional interrupts.
Once an interrupt is latched, no other interrupt can take
precedence, regardless of its priority.
• Loads the program counter with a user-defined vector address
Frees
cale Semiconductor,
I
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