Datasheet

Resets and Interrupts
Resets
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Resets and Interrupts 63
A power-on reset:
• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles
• Drives the RST pin low during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay
• Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay
• Sets the POR bit in the SIM reset status register and clears all
other bits in the register
Figure 4-2. Power-On Reset Recovery
4.3.3.2 COP Reset
A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the system integration module
(SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.
PORRST
(1)
OSC1
CGMXCLK
CGMOUT
RST
PIN
INTERNAL
4096
CYCLES
32
CYCLES
32
CYCLES
1. PORRST is an internally generated power-on reset pulse.
RESET
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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