Datasheet

Low Power Modes
Technical Data MC68HC908GR8 — Rev 4.0
52 Low Power Modes MOTOROLA
3.6 Clock Generator Module (CGM)
3.6.1 Wait Mode
The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.
3.6.2 Stop Mode
If the OSCSTOPEN bit in the CONFIG register is cleared (default), then
the STOP instruction disables the CGM (oscillator and phase-locked
loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).
If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.
If the OSCSTOPEN bit in the CONFIG register is set, then the phase
locked loop is shut off, but the oscillator will continue to operate in stop
mode.
3.7 Computer Operating Properly Module (COP)
3.7.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine
or a DMA service routine.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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