Datasheet

Memory Map
Technical Data MC68HC908GR8 — Rev 4.0
42 Memory Map MOTOROLA
$001E
Configuration Register 2
(CONFIG2)†
Read: 000000
OSC-
STOPENB
SCIBD-
SRC
Write:
Reset:00000000
$001F
Configuration Register 1
(CONFIG1)
†
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3
†
SSREC STOP COPD
Write:
Reset:00000000
$0020
Timer 1 Status and Control
Register (T1SC)
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
$0021
Timer 1 Counter Register
High (T1CNTH)
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:00000000
$0022
Timer 1 Counter Register
Low (T1CNTL)
Read: Bit 7 654321Bit 0
Write:
Reset:00000000
$0023
Timer 1 Counter Modulo
Register High (T1MODH)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset:11111111
$0024
Timer 1 Counter Modulo
Register Low (T1MODL)
Read:
Bit 7654321Bit 0
Write:
Reset:11111111
$0025
Timer 1 Channel 0 Status
and Control Register
(T1SC0)
Read: CH0F
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Write: 0
Reset:00000000
$0026
Timer 1 Channel 0
Register High (T1CH0H)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: Indeterminate after reset
$0027
Timer 1 Channel 0
Register Low (T1CH0L)
Read:
Bit 7654321Bit 0
Write:
Reset: Indeterminate after reset
† One-time writeable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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