Datasheet

Electrical Specifications
3.0 V Control Timing
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Electrical Specifications 369
23.8 3.0 V Control Timing
Table 23-7. 3.0 V Control Timing
Characteristic
(1)
1. V
SS
= 0 Vdc; timing shown with respect to 20% V
DD
and 70% V
SS
unless otherwise noted.
Symbol Min Max Unit
Frequency of operation
(2)
Crystal option
External clock option
(3)
2. See Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
f
osc
32
dc
(4)
4. Some modules may require a minimum frequency greater than dc for proper operation.
See appropriate table for this information.
100
16.4
kHz
MHz
Internal operating frequency
f
op
— 4.1 MHz
Internal clock period (1/f
OP
)t
cyc
244 — ns
RESET
input pulse width low
(5)
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse
width to cause a reset.
t
IRL
125 — ns
IRQ
interrupt pulse width low
(6)
(edge-triggered)
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
t
ILIH
125 — ns
IRQ
interrupt pulse period
t
ILIL
Note 8 —
t
cyc
16-bit timer
(7)
Input capture pulse width
Input capture period
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to
be recognized.
8. The minimum period, t
ILIL
or t
TLTL
, should not be less than the number of cycles it takes to
execute the interrupt service routine plus t
CYC
.
t
TH,
t
TL
t
TLTL
Note 8
—
—
ns
t
cyc
Notes:
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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