Datasheet

Timer Interface Module (TIM)
I/O Registers
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Timer Interface Module (TIM) 349
22.10 I/O Registers
NOTE: References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TSC may generically refer to
both T1SC AND T2SC.
These I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0, TSC1)
• TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
22.10.1 TIM Status and Control Register
The TIM status and control register (TSC):
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B
Bit 7654321Bit 0
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST
Reset:00100000
= Unimplemented
Figure 22-4. TIM Status and Control Register (TSC)
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