Datasheet

Timer Interface Module (TIM)
Technical Data MC68HC908GR8 — Rev 4.0
348 Timer Interface Module (TIM) MOTOROLA
22.8 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. See SIM Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
22.9 I/O Signals
Port D shares three of its pins with the TIM. (There is an optional TCLK
which can be used as an external clock input to the TIM prescaler, but is
not available on this MCU.) The three TIM channel I/O pins are T1CH0,
T1CH1 and T2CH0 as described in Pin Name Conventions.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.
Frees
cale Semiconductor,
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Freescale Semiconductor, Inc.
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