Datasheet

Serial Peripheral Interface (SPI)
Technical Data MC68HC908GR8 — Rev 4.0
324 Serial Peripheral Interface (SPI) MOTOROLA
SPE — SPI Enable
This read/write bit enables the SPI module. Clearing SPE causes a
partial reset of the SPI. See Resetting the SPI. Reset clears the SPE
bit.
1 = SPI module enabled
0 = SPI module disabled
SPTIE— SPI Transmit Interrupt Enable
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
20.14.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these
conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow
error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
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cale Semiconductor,
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