Datasheet

Serial Peripheral Interface (SPI)
Interrupts
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Serial Peripheral Interface (SPI) 315
Reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. The clearing mechanism
for the SPTE flag is always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, regardless of the state of the
SPE bit. See Figure 20-11.
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF bits to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error CPU interrupt requests.
Figure 20-11. SPI Interrupt Request Generation
SPTE SPTIE
SPRFSPRIE
DMAS
ERRIE
MODF
OVRF
SPE
CPU INTERRUPT REQUEST
CPU INTERRUPT REQUEST
NOT AVAILABLE
SPI TRANSMITTER
NOT AVAILABLE
SPI RECEIVER/ERROR
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