Datasheet

System Integration Module (SIM)
Exception Control
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA System Integration Module (SIM) 289
19.6.1.6 Interrupt Status Register 3
Bits 7–2 — Always read 0
I16–I15 — Interrupt Flags 16–15
These flags indicate the presence of an interrupt request from the
source shown in Table 19-3.
1 = Interrupt request present
0 = No interrupt request present
19.6.2 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
19.6.3 Break Interrupts
The break module can stop normal program flow at a software-
programmable break point by asserting its break interrupt output. See
Timer Interface Module (TIM). The SIM puts the CPU into the break state
by forcing it to the SWI vector location. Refer to the break interrupt
subsection of each module to see how each module is affected by the
break state.
Address: $FE06
Bit 7654321Bit 0
Read: 000000I16I15
Write:RRRRRRRR
Reset:00000000
R= Reserved
Figure 19-14. Interrupt Status Register 3 (INT3)
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