Datasheet

System Integration Module (SIM)
Technical Data MC68HC908GR8 — Rev 4.0
278 System Integration Module (SIM) MOTOROLA
then follows the sequence from the falling edge of RST shown in Figure
19-5.
Figure 19-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
Figure 19-6. Sources of Internal Reset
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
19.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 CGMXCLK cycles. Sixty-four CGMXCLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, these events occur:
• A POR pulse is generated.
IRST
RST
RST PULLED LOW BY MCU
IAB
32 CYCLES 32 CYCLES
VECTOR HIGH
CGMXCLK
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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