Datasheet

Input/Output Ports (I/O)
Port D
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Input/Output Ports (I/O) 223
Figure 16-15. Port D I/O Circuit
When bit DDRDx is a logic 1, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic 0, reading address $0003 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-5 summarizes
the operation of the port D pins.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
READ PTD ($0003)
PTDx
DDRDx
PTDx
INTERNAL DATA BUS
VDD
INTERNAL
PTDPUEx
PULLUP
DEVICE
Table 16-5. Port D Pin Functions
PTDPUE Bit DDRD Bit PTD Bit I/O Pin Mode
Accesses to DDRD Accesses to PTD
Read/Write Read Write
10
X
(1)
Input, V
DD
(4)
DDRD6–DDRD0 Pin
PTD6–PTD0
(3)
00X
Input, Hi-Z
(2)
DDRD6–DDRD0 Pin
PTD6–PTD0
(3)
X 1 X Output DDRD6–DDRD0 PTD6–PTD0 PTD6–PTD0
Notes:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V
DD
by internal pullup device.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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