Datasheet

Input/Output Ports (I/O)
Port A
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Input/Output Ports (I/O) 211
Figure 16-4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 16-2 summarizes
the operation of the port A pins.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
PTAx
DDRAx
PTAx
INTERNAL DATA BUS
V
DD
PTAPUEx
INTERNAL
PULLUP
DEVICE
Table 16-2. Port A Pin Functions
PTAPUE Bit DDRA Bit PTA Bit I/O Pin Mode
Accesses to DDRA Accesses to PTA
Read/Write Read Write
10
X
(1)
Input, V
DD
(4)
DDRA3–DDRA0 Pin
PTA3–PTA0
(3
)
00X
Input, Hi-Z
(2)
DDRA3–DDRA0 Pin
PTA3–PTA0
(3
)
X 1 X Output DDRA3–DDRA0 PTA3–PTA0 PTA3–PTA0
NOTES:
1. X = Don’t care
2. Hi-Z = High impedance
3. Writing affects data register, but does not affect input.
4. I/O pin pulled up to V
DD
by internal pullup device
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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