Datasheet

Input/Output Ports (I/O)
Technical Data MC68HC908GR8 — Rev 4.0
210 Input/Output Ports (I/O) MOTOROLA
16.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
DDRA3–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA3–DDRA0, configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 16-4 shows the port A I/O logic.
Address: $0004
Bit 7654321Bit 0
Read: 0000
DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
Figure 16-3. Data Direction Register A (DDRA)
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cale Semiconductor,
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