Datasheet

Monitor ROM (MON)
Functional Description
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Monitor ROM (MON) 193
If entering monitor mode with V
TST
applied on IRQ (condition set 1), the
CGMOUT frequency is equal to the CGMXCLK frequency and the OSC1
input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.
If entering monitor mode without high voltage applied on IRQ (condition
set 2 or 3, where applied voltage is either V
DD
or V
SS
), then all port B pin
Table 15-1. Monitor Mode Signal Requirements and Options
IRQ RESET
$FFFE/
$FFFF
PLL PTB0 PTB1
External
Clock
(1)
CGMOUT
Bus
Freq
COP
For Serial
Communication
Comment
PTA0 PTA1
Baud
Rate
(2) (3)
X GND X X X X X 0 0 Disabled X X 0
No operation until
reset goes high
V
TST
V
DD
or
V
TST
XOFF1 0
9.8304
MHz
4.9152
MHz
2.4576
MHz
Disabled
1 0 9600 PTB0 and PTB1
voltages only
required if
IRQ
=V
TST
X1DNA
V
DD
V
DD
$FFFF OFF X X
9.8304
MHz
4.9152
MHz
2.4576
MHz
Disabled
1 0 9600 External frequency
always divided by
4
X1DNA
GND
V
DD
$FFFF ON X X
32.768
kHz
4.9152
MHz
2.4576
MHz
Disabled
1 0 9600 PLL enabled (BCS
set) in monitor
code
X1DNA
V
DD
or
GND
V
TST
$FFFF OFF X X X ——Enabled X X —
Enters user mode
— will encounter
an illegal address
reset
V
DD
or
GND
V
DD
or
V
TST
Not
$FFFF
OFF X X X ——Enabled X X — Enters user mode
Notes:
1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator
2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication
3. PTA1 = 0 → serial, PTA1 = 1 → parallel communication for security code entry
4. DNA = does not apply, X = don’t care
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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