Datasheet

Low-Voltage Inhibit (LVI)
LVI Status Register
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Low-Voltage Inhibit (LVI) 187
14.4.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is
configured for 5V or 3V protection.
NOTE: The microcontroller is guaranteed to operate at a minimum supply
voltage. The trip point (V
TRIPF
[5 V] or V
TRIPF
[3 V]) may be lower than
this. (See Electrical Specifications for the actual trip point voltages.)
14.5 LVI Status Register
The LVI status register (LVISR) indicates if the V
DD
voltage was
detected below the V
TRIPF
level.
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
DD
voltage falls below the
V
TRIPF
trip voltage. See Table 14-1. Reset clears the LVIOUT bit.
Address: $FE0C
Bit 7654321Bit 0
Read: LVIOUT 0000000
Write:
Reset:00000000
= Unimplemented
Figure 14-3. LVI Status Register (LVISR)
Table 14-1. LVIOUT Bit Indication
V
DD
LVIOUT
V
DD
> V
TRIPR
0
V
DD
< V
TRIPF
1
V
TRIPF
< V
DD
< V
TRIPR
Previous value
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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