Datasheet

Low-Voltage Inhibit (LVI)
Technical Data MC68HC908GR8 — Rev 4.0
186 Low-Voltage Inhibit (LVI) MOTOROLA
14.4.1 Polled LVI Operation
In applications that can operate at V
DD
levels below the V
TRIPF
level,
software can monitor V
DD
by polling the LVIOUT bit. In the configuration
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
14.4.2 Forced Reset Operation
In applications that require V
DD
to remain above the V
TRIPF
level,
enabling LVI resets allows the LVI module to reset the MCU when V
DD
falls below the V
TRIPF
level. In the configuration register, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
14.4.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V
DD
fall below V
TRIPF
), the LVI
will maintain a reset condition until V
DD
rises above the rising trip point
voltage, V
TRIPR
. This prevents a condition in which the MCU is
continually entering and exiting reset if V
DD
is approximately equal to
V
TRIPF
. V
TRIPR
is greater than V
TRIPF
by the hysteresis voltage, V
HYS
.
Addr.Register Name Bit 7654321Bit 0
$FE0C
LVI Status Register
(LVISR)
Read: LVIOUT 0000000
Write:
Reset:00000000
= Unimplemented
Figure 14-2. LVI I/O Register Summary
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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