Datasheet

Low-Voltage Inhibit (LVI)
Functional Description
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Low-Voltage Inhibit (LVI) 185
LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration
register (MOR1). See Configuration Register (CONFIG) for details of the
LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in
reset until V
DD
rises above a voltage, V
TRIPR
, which causes the MCU to
exit reset. See Low-Voltage Inhibit (LVI) Reset for details of the
interaction between the SIM and the LVI. The output of the comparator
controls the state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
Figure 14-1. LVI Module Block Diagram
LOW V
DD
DETECTOR
LVIPWRD
STOP INSTRUCTION
LVISTOP
LVI RESET
LVIOUT
V
DD
> LVI
Trip
= 0
V
DD
≤ LVI
Trip
= 1
FROM CONFIG
FROM CONFIG
V
DD
FROM CONFIG
LVIRSTD
LVI5OR3
FROM CONFIG
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cale Semiconductor,
I
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