Datasheet

Low-Voltage Inhibit (LVI)
Technical Data MC68HC908GR8 — Rev 4.0
184 Low-Voltage Inhibit (LVI) MOTOROLA
14.4 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor V
DD
voltage. Clearing the LVI reset disable bit, LVIRSTD,
enables the LVI module to generate a reset when V
DD
falls below the trip
point voltage, V
TRIPF
. Setting the LVI enable in stop mode bit, LVISTOP,
enables the LVI to operate in stop mode. Setting the LVI 5V or 3V trip
point bit, LVI5OR3, enables V
TRIPF
to be configured for 5V operation.
Clearing the LVI5OR3 bit enables V
TRIPF
to be configured for 3V
operation. The actual trip points are shown in Electrical Specifications.
NOTE: After a power-on reset (POR) the LVI’s default mode of operation is 3 V.
If a 5V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5V operation. Note that this must be done after every POR since
the default will revert back to 3V mode after each POR. If the V
DD
supply
is below the 5V mode trip voltage but above the 3V mode trip voltage
when POR is released, the part will operate because V
TRIPF
defaults to
3V mode after a POR. So, in a 5V system care must be taken to ensure
that V
DD
is above the 5V mode trip voltage after POR is released.
NOTE: If the user requires 5V mode and sets the LVI5OR3 bit after a POR while
the V
DD
supply is not above the V
TRIPR
for 5V mode, the MCU will
immediately go into reset. The LVI in this case will hold the part in reset
until either V
DD
goes above the rising 5V trip point, V
TRIPR
, which will
release reset or V
DD
decreases to approximately 0 V which will re-trigger
the POR and reset the trip point to 3V operation.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
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