Datasheet

External Interrupt (IRQ)
IRQ Module During Break Interrupts
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA External Interrupt (IRQ) 171
The IRQF bit in the INTSCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
12.6 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latch during the break state. See Break Module
(BRK).
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ interrupt flags.
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