Datasheet

Central Processing Unit (CPU)
Technical Data MC68HC908GR8 — Rev 4.0
154 Central Processing Unit (CPU) MOTOROLA
10.9 Opcode Map
See Table 10-2.
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 ––↕↕–
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
ff
3
1
1
3
2
4
TSX Transfer SP to H:X H:X
← (SP) + 1 ––––––INH 95 2
TXA Transfer X to A A
← (X) ––––––INH 9F 1
TXS Transfer H:X to SP (SP)
← (H:X) – 1 ––––––INH 94 2
A Accumulatorn Any bit
C Carry/borrow bitopr Operand (one or two bytes)
CCRCondition code registerPC Program counter
ddDirect address of operandPCH Program counter high byte
dd rrDirect address of operand and relative offset of branch instructionPCL Program counter low byte
DDDirect to direct addressing modeREL Relative addressing mode
DIRDirect addressing moderel Relative program counter offset byte
DIX+Direct to indexed with post increment addressing moderr Relative program counter offset byte
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1 Stack pointer, 8-bit offset addressing mode
EXTExtended addressing modeSP2 Stack pointer 16-bit offset addressing mode
ff Offset byte in indexed, 8-bit offset addressingSP Stack pointer
H Half-carry bitU Undefined
H Index register high byteV Overflow bit
hh llHigh and low bytes of operand address in extended addressingX Index register low byte
I Interrupt maskZ Zero bit
ii Immediate operand byte& Logical AND
IMDImmediate source to direct destination addressing mode| Logical OR
IMMImmediate addressing mode
⊕ Logical EXCLUSIVE OR
INHInherent addressing mode( ) Contents of
IXIndexed, no offset addressing mode–( ) Negation (two’s complement)
IX+Indexed, no offset, post increment addressing mode# Immediate value
IX+DIndexed with post increment to direct addressing mode
« Sign extend
IX1Indexed, 8-bit offset addressing mode
← Loaded with
IX1+Indexed, 8-bit offset, post increment addressing mode? If
IX2Indexed, 16-bit offset addressing mode: Concatenated with
MMemory location↕ Set or cleared
N Negative bit— Not affected
Table 10-1. Instruction Set Summary (Continued)
Source
Form
Operation Description
Effect on
CCR
Address Mode Opcode Operand Cycles
VH I NZC
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