Datasheet

Central Processing Unit (CPU)
Technical Data MC68HC908GR8 — Rev 4.0
146 Central Processing Unit (CPU) MOTOROLA
10.6.1 WAIT mode
The WAIT instruction:
• clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from WAIT mode by interrupt, the I
bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
10.6.2 STOP mode
The STOP instruction:
• clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from STOP mode by
external interrupt, the I bit remains clear. After exit by reset, the I
bit is set.
• Disables the CPU clock
After exiting STOP mode, the CPU clock begins running after the
oscillator stabilization delay.
10.7 CPU during break interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See Break Module (BRK). The program counter
vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
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