Datasheet

Computer Operating Properly (COP)
Technical Data MC68HC908GR8 — Rev 4.0
134 Computer Operating Properly (COP) MOTOROLA
Figure 9-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2
18
– 2
4
or 2
13
– 2
4
CGMXCLK cycles, depending on the state of the COP rate select bit,
COPRS, in the configuration register. With a 2
13
– 2
4
CGMXCLK cycle
overflow option, a 32.768-kHz crystal gives a COP timeout period of
250 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12
through 5 of the prescaler.
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).
COPCTL WRITE
CGMXCLK
RESET VECTOR FETCH
RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES
CLEAR STAGES 5–12
12-BIT COP PRESCALER
CLEAR ALL STAGES
6-BIT COP COUNTER
COP DISABLE
RESET
COPCTL WRITE
CLEAR
COP MODULE
COPEN (FROM SIM)
COP COUNTER
COP CLOCK
COP TIMEOUT
STOP INSTRUCTION
(FROM CONFIG)
COP RATE SEL
(FROM CONFIG)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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