Datasheet

Configuration Register (CONFIG)
Technical Data MC68HC908GR8 — Rev 4.0
132 Configuration Register (CONFIG) MOTOROLA
LVI5OR3 — LVI 5V or 3V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. See
Low-Voltage Inhibit (LVI). The voltage mode selected for the LVI
should match the operating V
DD
. See Electrical Specifications for the
LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5V mode.
0 = LVI operates in 3V mode.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.
NOTE: When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a
delay longer than the enable time for the LVI. There is no period where
the MCU is not protected from a low power condition. However, when
using the short stop recovery configuration option, the 32-CGMXCLK
delay is less than the LVI’s turn-on time and there exists a period in
startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Computer Operating Properly
(COP).
1 = COP module disabled
0 = COP module enabled
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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