Datasheet

Clock Generator Module (CGMC)
CGMC Registers
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Clock Generator Module (CGMC) 119
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
ACQ — Acquisition Mode Bit
When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.
1 = Tracking mode
0 = Acquisition mode
7.6.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the
programming information for the high byte of the modulo feedback
divider.
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback
divider that selects the VCO frequency multiplier N. (See PLL Circuits
and Programming the PLL.) A value of $0000 in the multiplier select
registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the registers to $0040 for a default multiply
value of 64.
Address: $0038
Bit 7654321Bit 0
Read: 0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
= Unimplemented
Figure 7-6. PLL Multiplier Select Register High (PMSH)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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