Datasheet

Clock Generator Module (CGMC)
CGMC Registers
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Clock Generator Module (CGMC) 117
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. (See Base Clock Selector Circuit.)
PRE1 and PRE0 — Prescaler Program Bits
These read/write bits control a prescaler that selects the prescaler
power-of-two multiplier, P. (See PLL Circuits and Programming the
PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set.
Reset clears these bits.
NOTE: The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.
VPR1 and 0 — VCO Power-of-Two Range Select Bits
These read/write bits control the VCO’s hardware power-of-two range
multiplier E that, in conjunction with L (See PLL Circuits,
Programming the PLL, and PLL VCO Range Select Register.)
controls the hardware center-of-range frequency, f
VRS
. VPR1:VPR0
cannot be written when the PLLON bit is set. Reset clears these bits.
Table 7-2. PRE 1 and PRE0 Programming
PRE1 and PRE0 P Prescaler Multiplier
00 0 1
01 1 2
10 2 4
11 3 8
Table 7-3. VPR1 and VPR0 Programming
VPR1 and VPR0 E
VCO Power-of-Two
Range Multiplier
00 0 1
01 1 2
10 2 4
11
3
(1)
1. Do not program E to a value of 3.
8
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cale Semiconductor,
I
Freescale Semiconductor, Inc.
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