Datasheet

Clock Generator Module (CGMC)
CGMC Registers
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Clock Generator Module (CGMC) 115
7.6.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
$003A
PLL VCO Select Range
Register (PMRS)
Read:
VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0
Write:
Reset:01000000
$003B
PLL Reference Divider
Select Register (PMDS)
Read: 0000
RDS3 RDS2 RDS1 RDS0
Write:
Reset:00000001
= Unimplemented R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ
is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 7-3. CGMC I/O Register Summary
Address: $0036
Bit 7654321Bit 0
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset:00100000
= Unimplemented
Figure 7-4. PLL Control Register (PCTL)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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