Datasheet

Clock Generator Module (CGMC)
Technical Data MC68HC908GR8 — Rev 4.0
114 Clock Generator Module (CGMC) MOTOROLA
7.6 CGMC Registers
These registers control and monitor operation of the CGMC:
• PLL control register (PCTL)
(See PLL Control Register.)
• PLL bandwidth control register (PBWC)
(See PLL Bandwidth Control Register.)
• PLL multiplier select register high (PMSH)
(See PLL Multiplier Select Register High.)
• PLL multiplier select register low (PMSL)
(See PLL Multiplier Select Register Low.)
• PLL VCO range select register (PMRS)
(See PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See PLL Reference Divider Select Register.)
Figure 7-3 is a summary of the CGMC registers.
Addr.Register Name Bit 7654321Bit 0
$0036
PLL Control Register
(PCTL)
Read:
PLLIE
PLLF
PLLON BCS PRE1 PRE0 VPR1 VPR0
Write:
Reset:00100000
$0037
PLL Bandwidth Control
Register (PBWC)
Read:
AUTO
LOCK
ACQ
0000
R
Write:
Reset:00000000
$0038
PLL Multiplier Select High
Register (PMSH)
Read: 0000
MUL11 MUL10 MUL9 MUL8
Write:
Reset:00000000
$0039
PLL Multiplier Select Low
Register (PMSL)
Read:
MUL7 MUL6 MUL5 MUL4 MUL3 MUL2 MUL1 MUL0
Write:
Reset:01000000
Figure 7-3. CGMC I/O Register Summary
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cale Semiconductor,
I
Freescale Semiconductor, Inc.
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