Datasheet

Clock Generator Module (CGMC)
Technical Data MC68HC908GR8 — Rev 4.0
112 Clock Generator Module (CGMC) MOTOROLA
7.5 I/O Signals
The following paragraphs describe the CGMC I/O signals.
7.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is an input to the crystal oscillator amplifier.
7.5.2 Crystal Amplifier Output Pin (OSC2)
The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.5.3 External Filter Capacitor Pin (CGMXFC)
The CGMXFC pin is required by the loop filter to filter out phase
corrections. An external filter network is connected to this pin. (See
Figure 7-2.)
NOTE: To prevent noise problems, the filter network should be placed as close
to the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.
7.5.4 PLL Analog Power Pin (V
DDA
)
V
DDA
is a power pin used by the analog portions of the PLL. Connect the
V
DDA
pin to the same voltage potential as the V
DD
pin.
NOTE: Route V
DDA
carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
7.5.5 PLL Analog Ground Pin (V
SSA
)
V
SSA
is a ground pin used by the analog portions of the PLL. Connect
the V
SSA
pin to the same voltage potential as the V
SS
pin.
NOTE: Route V
SSA
carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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