Datasheet

Clock Generator Module (CGMC)
Functional Description
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Clock Generator Module (CGMC) 109
c. In the PLL multiplier select register low (PMSL) and the PLL
multiplier select register high (PMSH), program the binary
equivalent of N.
d. In the PLL VCO range select register (PMRS), program the
binary coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program
the binary coded equivalent of R.
Table 7-1 provides numeric examples (numbers are in hexadecimal
notation):
7.4.7 Special Programming Exceptions
The programming method described in Programming the PLL does not
account for three possible exceptions. A value of 0 for R, N, or L is
meaningless when used in the equations given. To account for these
exceptions:
• A 0 value for R or N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the
source for the base clock.
(See Base Clock Selector Circuit.)
Table 7-1. Numeric Example
f
BUS
f
RCLK
RNPEL
2.0 MHz 32.768 kHz 1 F5 0 0 D1
2.4576 MHz 32.768 kHz 1 12C 0 1 80
2.5 MHz 32.768 kHz 1 132 0 1 83
4.0 MHz 32.768 kHz 1 1E9 0 1 D1
4.9152 MHz 32.768 kHz 1 258 0 2 80
5.0 MHz 32.768 kHz 1 263 0 2 82
7.3728 MHz 32.768 kHz 1 384 0 2 C0
8.0 MHz 32.768 kHz 1 3D1 0 2 D0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...