Datasheet

Clock Generator Module (CGMC)
Technical Data MC68HC908GR8 — Rev 4.0
108 Clock Generator Module (CGMC) MOTOROLA
this table:
8. Select a VCO linear range multiplier, L, where f
NOM
= 38.4 kHz
9. Calculate and verify the adequacy of the VCO programmed
center-of-range frequency, f
VRS
. The center-of-range frequency is
the midpoint between the minimum and maximum frequencies
attainable by the PLL.
For proper operation,
10. Verify the choice of P, R, N, E, and L by comparing f
VCLK
to f
VRS
and f
VCLKDES
. For proper operation, f
VCLK
must be within the
application’s tolerance of f
VCLKDES
, and f
VRS
must be as close as
possible to f
VCLK
.
NOTE: Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program
the binary equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program
the binary equivalent of E.
Frequency Range E
0 < f
VCLK
< 9,830,400
0
9,830,400 ≤ f
VCLK
< 19,660,800
1
19,660,800 ≤ f
VCLK
< 39,321,600
2
NOTE: Do not program E to a value of 3.
L round
f
VCLK
2
E
f
NOM
×
--------------------------



=
f
VRS
L2
E
×()f
NOM
=
f
VRS
f
VCLK
–
f
NOM
2
E
×
2
--------------------------
≤
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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