Datasheet

Clock Generator Module (CGMC)
Functional Description
MC68HC908GR8 — Rev 4.0 Technical Data
MOTOROLA Clock Generator Module (CGMC) 105
to use as the source for the base clock. (See Base Clock Selector
Circuit.) If the VCO is selected as the source for the base clock and the
LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See Interrupts for information and precautions on using interrupts.)
The following conditions apply when the PLL is in automatic bandwidth
control mode:
• The ACQ bit (see PLL Bandwidth Control Register) is a read-only
indicator of the mode of the filter. (See Acquisition and Tracking
Modes.)
• The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See Acquisition/Lock Time Specifications for
more information.)
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See Acquisition/Lock Time Specifications for
more information.)
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See PLL Control
Register.)
The PLL also may operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below f
BUSMAX
.
The following conditions apply when in manual mode:
• ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, t
ACQ
(see Acquisition/Lock Time Specifications), after
turning on the PLL by setting PLLON in the PLL control register
(PCTL).
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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