Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 32 (7x7) 8-Bit 8 MHz I/O number 21

WWW.MOTOROLA.COM/SEMICONDUCTORS

M68HC08

Microcontrollers

MC68HC908GR8/D

Rev. 4, 6/2002

MC68HC908GR8

Technical Data

MC68HC908GR4

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

Summary of content (408 pages)

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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MC68HC908GR8 MC68HC908GR4 Technical Data M68HC08 Microcontrollers MC68HC908GR8/D Rev. 4, 6/2002 WWW.MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MC68HC908GR8 MC68HC908GR4 Technical Data — Rev 4.0 Motorola reserves the right to make changes without further notice to any products herein.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data MC68HC908GR8 — Rev 4.0 4 MOTOROLA For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 List of Paragraphs List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Freescale Semiconductor, Inc... Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Section 1. General Description . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Paragraphs Section 17. RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Section 18. Serial Communications Interface (SCI) . . . 231 Section 19. System Integration Module (SIM) . . . . . . . 271 Section 20. Serial Peripheral Interface (SPI). . . . . . . . . 297 Section 21. Timebase Module (TBM) . . . . . . . . . . . . . . . 329 Section 22. Timer Interface Module (TIM) . . . . . . . . . . . 335 Freescale Semiconductor, Inc... Section 23.
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Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Table of Contents List of Paragraphs Freescale Semiconductor, Inc... Table of Contents List of Tables List of Figures Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Section 3. Low Power Modes 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 50 3.4 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.
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Freescale Semiconductor, Inc. Table of Contents 5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 5.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Section 8. Configuration Register (CONFIG) 8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Freescale Semiconductor, Inc... Section 9. Computer Operating Properly (COP) 9.1 Contents . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Section 11. Flash Memory 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.
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Freescale Semiconductor, Inc. Table of Contents 13.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 13.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .180 13.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Freescale Semiconductor, Inc... Section 14. Low-Voltage Inhibit (LVI) 14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.
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Freescale Semiconductor, Inc. Table of Contents 16.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Section 17. RAM 17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Freescale Semiconductor, Inc... Section 18.
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Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Section 20. Serial Peripheral Interface (SPI) 20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 20.4 Pin Name Conventions and I/O Register Addresses . . . . . . . 298 20.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table of Contents 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 22.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 22.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 22.6 Interrupts. . . . . . . . . . . .
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Freescale Semiconductor, Inc. Table of Contents 23.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . . 383 23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 Freescale Semiconductor, Inc... Section 24. Mechanical Specifications 24.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.
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Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 List of Tables Table Freescale Semiconductor, Inc... 2-1 4-1 4-2 5-1 5-2 7-1 7-2 7-3 10-1 10-2 11-1 14-1 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 16-1 16-2 16-3 16-4 16-5 16-6 18-1 18-2 Title Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Tables Freescale Semiconductor, Inc... 18-3 18-4 18-5 18-6 18-7 18-8 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 21-1 22-1 22-2 22-3 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 25-1 25-2 25-3 Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 List of Figures Figure Freescale Semiconductor, Inc... 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 7-3 Title MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DIP And SOIC Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... 7-4 7-5 7-6 7-7 7-8 7-9 7-10 8-1 8-2 9-1 9-2 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 11-4 12-1 12-2 12-3 13-1 13-2 13-3 13-4 14-1 14-2 14-3 15-1 15-2 15-3 15-4 15-5 15-6 15-7 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 115 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . . 118 PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... 15-8 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 19-1 19-2 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 203 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Port A Data Register (PTA) . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 19-18 19-19 19-20 19-21 19-22 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 21-1 21-2 22-1 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Internal Reset Timing . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Figures TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 343 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 349 TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . . 352 TIM Counter Registers Low (TCNTL) . . . . . . . . . . . . . . . . . . . 352 TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... 23-12 Typical Low-Side Driver Characteristics – Ports PTB5–PTB0, PTD6–PTD0, and PTE1–PTE0 (VDD = 2.7 Vdc) . . . . . . . . . . 375 23-13 Typical Operating IDD, with All Modules Turned On (–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 23-14 Typical Wait Mode IDD, with all Modules Disabled (–40 °C to 125 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. General Description 1.3 Features For convenience, features have been organized to reflect: • Standard features of the MC68HC908GR8 • Features of the CPU08 Freescale Semiconductor, Inc... 1.3.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description • 4-bit keyboard wakeup port • 32-pin quad flat pack (QFP) or 28-pin plastic dual-in-line package (DIP) or 28-pin small outline integrated circuit (SOIC) • Specific features of the MC68HC908GR8 in 28-pin DIP and 28-pin SOIC are: – Port B is only 4 bits: PTB0–PTB3; 4-channel ADC module – No Port C bits 1.3.
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ARITHMETIC/LOGIC UNIT (ALU) MC68HC908GR8 — Rev 4.0 General Description For More Information On This Product, Go to: www.freescale.com * IRQ POWER † Ports are software configurable with pullup device if input port.
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Freescale Semiconductor, Inc. General Description OSC2 CGMXFC VSSA VDDA PTC1 PTC0 PTA3/KBD3 30 29 28 27 26 25 1 24 PTA2/KBD2 VDDAD/VREFH PTD1/MISO 6 19 PTB5/AD5 PTD2/MOSI 7 18 PTB4/AD4 PTD3/SPSCK 8 17 PTB3/AD3 16 20 PTB2/AD2 5 15 PTD0/SS PTB1/AD1 VSSAD/VREFL 14 21 PTB0/AD0 4 13 IRQ PTD6/T2CH0 PTA0/KBD0 12 22 PTD5/T1CH1 3 11 PTE1/RxD PTD4/T1CH0 PTA1/KBD1 10 23 VDD 2 9 PTE0/TxD VSS Freescale Semiconductor, Inc... RST 31 32 OSC1 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description MCU VDD VSS C1 0.1 µF + C2 VDD NOTE: Component values shown represent typical applications. Figure 1-4. Power Supply Bypassing 1.6.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Clock Generator Module (CGMC). 1.6.3 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known startup state.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description Pin Functions 1.6.6 External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Clock Generator Module (CGMC). 1.6.7 Analog Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL) VDDAD and VSSAD are the power supply pins for the analog-to-digital converter. Decoupling of these pins should be as per the digital supply. NOTE: VREFH is the high reference supply for the ADC.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description 1.6.10 Port C I/O Pins (PTC1–PTC0) PTC1–PTC0 are general-purpose, bidirectional I/O port pins. See Input/Output Ports (I/O). PTC0 and PTC1 are only available on 32-pin QFP packages. These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. 1.6.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 2. Memory Map 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . 35 2.4 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.5 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.
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Freescale Semiconductor, Inc. Memory Map 2.4 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In the Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R. 2.5 Input/Output (I/O) Section Freescale Semiconductor, Inc... Most of the control, status, and data registers are in the zero page area of $0000–$003F.
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Freescale Semiconductor, Inc. Memory Map Input/Output (I/O) Section $0000 I/O Registers 64 Bytes ↓ $003F $0040 RAM 384 Bytes ↓ $01BF $01C0 Unimplemented 6720 Bytes Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Memory Map $FE08 FLASH Control Register (FLCR) $FE09 Break Address Register High (BRKH) $FE0A Break Address Register Low (BRKL) $FE0B Break Status and Control Register (BRKSCR) $FE0C LVI Status Register (LVISR) $FE0D ↓ Reserved 3 Bytes Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Memory Map Input/Output (I/O) Section Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Memory Map Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Memory Map Input/Output (I/O) Section Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Memory Map Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Memory Map Input/Output (I/O) Section Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Memory Map Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Memory Map Input/Output (I/O) Section Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Memory Map Addr.
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Freescale Semiconductor, Inc. Memory Map Input/Output (I/O) Section . Table 2-1. Vector Addresses Vector Priority Lowest Vector IF16 IF15 IF14 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Memory Map Technical Data 48 MC68HC908GR8 — Rev 4.0 Memory Map For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 3. Low Power Modes Freescale Semiconductor, Inc... 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 50 3.4 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.5 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low Power Modes 3.2.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the CPU clock is disabled but the bus clock continues to run. Power consumption can be further reduced by disabling the LVI module and/or the timebase module through bits in the CONFIG register. (See Configuration Register (CONFIG).) 3.2.2 Stop Mode Stop mode is entered when a STOP instruction is executed.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low Power Modes Break Module (BRK) 3.4 Break Module (BRK) 3.4.1 Wait Mode If enabled, the break module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the BW bit in the break status register is set. 3.4.2 Stop Mode The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the BW bit in the break status register.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low Power Modes 3.6 Clock Generator Module (CGM) 3.6.1 Wait Mode The CGM remains active in wait mode. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low Power Modes External Interrupt Module (IRQ) 3.7.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the configuration register (CONFIG) enables the STOP instruction.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low Power Modes 3.9.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. 3.10 Low-Voltage Inhibit Module (LVI) 3.10.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 3.10.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low Power Modes Serial Peripheral Interface Module (SPI) 3.11.2 Stop Mode The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data. 3.12 Serial Peripheral Interface Module (SPI) 3.12.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low Power Modes 3.13.2 Stop Mode The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt. 3.14 Timebase Module (TBM) 3.14.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU.
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Freescale Semiconductor, Inc. Low Power Modes Exiting Wait Mode 3.15 Exiting Wait Mode Freescale Semiconductor, Inc... These events restart the CPU clock and load the program counter with the reset vector or with an interrupt vector: • External reset — A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Low Power Modes • Low-voltage inhibit (LVI) reset — A power supply voltage below the LVItripf voltage resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. • Break interrupt — A break interrupt loads the program counter with the contents of locations $FFFC and $FFFD.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Low Power Modes Technical Data 60 MC68HC908GR8 — Rev 4.0 Low Power Modes For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 4. Resets and Interrupts 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts 4.3.2 External Reset A logic 0 applied to the RST pin for a time, tIRL, generates an external reset. An external reset sets the PIN bit in the SIM reset status register. 4.3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts 4.3.3.3 Low-Voltage Inhibit Reset A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the LVI trip voltage, VTRIPF.
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Freescale Semiconductor, Inc. Resets and Interrupts Resets 4.3.4 SIM Reset Status Register This read-only register contains flags to show reset sources. All flag bits are automatically cleared following a read of the register. Reset service can read the SIM reset status register to clear the register after poweron reset and to determine the source of any subsequent reset. Freescale Semiconductor, Inc... The register is initialized on powerup as shown with the POR bit set and all other bits cleared.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts ILOP — Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD — Illegal Address Reset Bit 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by low-power supply voltage 0 = POR or read of SRSR 4.
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Freescale Semiconductor, Inc. Resets and Interrupts Interrupts • • Freescale Semiconductor, Inc... • 5 CONDITION CODE REGISTER 1 4 ACCUMULATOR 2 INDEX REGISTER (LOW BYTE)* STACKING 3 ORDER 2 PROGRAM COUNTER (HIGH BYTE) 3 UNSTACKING ORDER 4 1 PROGRAM COUNTER (LOW BYTE) 5 • • • $00FF DEFAULT ADDRESS ON RESET *High byte of index register is not stacked. Figure 4-4. Interrupt Stacking Order After every instruction, the CPU checks all pending interrupts if the I bit is not set.
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Freescale Semiconductor, Inc. Resets and Interrupts CLI BACKGROUND ROUTINE LDA #$FF INT1 PSHH INT1 INTERRUPT SERVICE ROUTINE Freescale Semiconductor, Inc... PULH RTI INT2 PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 4-5. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation.
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Freescale Semiconductor, Inc. Resets and Interrupts Interrupts FROM RESET BREAK INTERRUPT ? NO YES YES BIT SET? SET? II BIT NO Freescale Semiconductor, Inc... IRQ INTERRUPT ? YES NO CGM INTERRUPT ? NO YES OTHER INTERRUPTS ? YES NO STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI YES INSTRUCTION ? NO RTI YES INSTRUCTION ? UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 4-6. Interrupt Processing MC68HC908GR8 — Rev 4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts 4.4.2 Sources The sources in Table 4-1 can generate CPU interrupt requests. Table 4-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts Interrupts 4.4.2.1 SWI Instruction The software interrupt instruction (SWI) causes a non-maskable interrupt. NOTE: A software interrupt pushes PC onto the stack. An SWI does not push PC – 1, as a hardware interrupt does. 4.4.2.2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software-programmable break point. 4.4.2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts 4.4.2.6 TIM2 TIM2 CPU interrupt sources: • TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value rolls over to $0000 after matching the value in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE, enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status and control register.
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Freescale Semiconductor, Inc. Resets and Interrupts Interrupts • Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE, enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control register. 4.4.2.8 SCI Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts • Noise flag (NF) — NF is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control register 3. • Framing error bit (FE) — FE is set when a logic 0 occurs where the receiver expects a stop bit.
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Freescale Semiconductor, Inc. Resets and Interrupts Interrupts 4.4.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 4-2 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 4-2. Interrupt Source Flags Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts 4.4.3.1 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: IF6 IF5 IF4 IF3 IF2 IF1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 4-7. Interrupt Status Register 1 (INT1) IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Table 4-2.
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Freescale Semiconductor, Inc. Resets and Interrupts Interrupts 4.4.3.3 Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 IF16 IF15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Freescale Semiconductor, Inc... Figure 4-9. Interrupt Status Register 3 (INT3) IF16–IF15 — Interrupt Flags 16–15 This flag indicates the presence of an interrupt request from the source shown in Table 4-2.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Resets and Interrupts Technical Data 78 MC68HC908GR8 — Rev 4.0 Resets and Interrupts For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 5. Analog-to-Digital Converter (ADC) 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 5.3 Features Features of the ADC module include: • Six channels with multiplexed input • Linear successive approximation with monotonicity • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • Selectable ADC clock 5.4 Functional Description The ADC provides six pins for sampling external sources at pins PTB5/ATD5–PTB0/ATD0.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) Functional Description INTERNAL DATA BUS READ DDRBx WRITE DDRBx DISABLE DDRBx RESET WRITE PTBx PTBx PTBx ADC CHANNEL x READ PTBx DISABLE ADC DATA REGISTER CONVERSION INTERRUPT COMPLETE LOGIC AIEN ADC ADC VOLTAGE IN ADCH4–ADCH0 (VADIN) CHANNEL SELECT ADC CLOCK COCO CGMXCLK BUS CLOCK CLOCK GENERATOR ADIV2–ADIV0 ADICLK Figure 5-1. ADC Block Diagram 5.4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 5.4.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $FF (full scale). If the input voltage equals VREFL, the ADC converts it to $00. Input voltages between VREFH and VREFL are a straight-line linear conversion. All other input voltages will result in $FF, if greater than VREFH.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) Interrupts 5.4.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. 5.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a DMA interrupt is generated.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 5.7.1 ADC Analog Power Pin (VDDAD)/ADC Voltage Reference High Pin (VREFH) The ADC analog portion uses VDDAD as its power pin. Connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. NOTE: For maximum noise immunity, route VDDAD carefully and place bypass capacitors as close as possible to the package. 5.7.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) I/O Registers 5.8 I/O Registers These I/O registers control and monitor ADC operation: • ADC status and control register (ADSCR) • ADC data register (ADR) • ADC clock register (ADCLK) Freescale Semiconductor, Inc... 5.8.1 ADC Status and Control Register Function of the ADC status and control register (ADSCR) is described here.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO — ADC Continuous Conversion Bit Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) I/O Registers Table 5-1.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) 5.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: $0003E Bit 7 6 5 4 ADIV2 ADIV1 ADIV0 ADICLK 0 0 0 0 Read: 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Write: Freescale Semiconductor, Inc... Reset: = Unimplemented Figure 5-4.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter (ADC) I/O Registers If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. 1 = Internal bus clock 0 = External clock (CGMXCLK) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Analog-to-Digital Converter (ADC) Technical Data 90 MC68HC908GR8 — Rev 4.0 Analog-to-Digital Converter (ADC) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 6. Break Module (BRK) 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Break Module (BRK) 6.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The CPU then loads the instruction register with a software interrupt instruction (SWI) after completion of the current CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Break Module (BRK) Functional Description Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Break Module (BRK) The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. 6.4.3 TIMI and TIM2 During Break Interrupts A break interrupt stops the timer counters. 6.4.4 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin. 6.
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Freescale Semiconductor, Inc. Break Module (BRK) Break Module Registers • Break address register low (BRKL) • SIM break status register (SBSR) • SIM break flag control register (SBFCR) 6.6.1 Break Status and Control Register Freescale Semiconductor, Inc... The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0E Bit 7 6 BRKE BRKA 0 0 Read: 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 Write: Reset: = Unimplemented Figure 6-3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Break Module (BRK) 6.6.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: $FE09 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 6-4.
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Freescale Semiconductor, Inc. Break Module (BRK) Break Module Registers BW — Break Wait Bit This read/write bit is set when a break interrupt causes an exit from wait mode. Clear BW by writing a logic 0 to it. Reset clears BW. 1 = Break interrupt during wait mode 0 = No break interrupt during wait mode BW can be read within the break interrupt routine. The user can modify the return address on the stack by subtracting 1 from it. The following code is an example. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Break Module (BRK) 6.6.4 Break Flag Control Register The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. Address: $FE03 Bit 7 6 5 4 3 2 1 Bit 0 BCFE R R R R R R R Read: Write: Freescale Semiconductor, Inc... Reset: 0 R = Reserved Figure 6-7.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 7. Clock Generator Module (CGMC) 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.4.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Functional Description The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGM/XFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (38.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison. 7.4.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Functional Description to use as the source for the base clock. (See Base Clock Selector Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. (See Interrupts for information and precautions on using interrupts.) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) • Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). • The LOCK bit is disabled. • CPU interrupts from the CGMC are disabled. 7.4.6 Programming the PLL Freescale Semiconductor, Inc... The following procedure shows how to program the PLL.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Functional Description allows. See Electrical Specifications. Choose the reference divider, R = 1. After choosing N and P, the actual bus frequency can be determined using equation in 2 above. When the tolerance on the bus frequency is tight, choose fRCLK to an integer divisor of fBUSDES, and R = 1.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) this table: Frequency Range E 0 < fVCLK < 9,830,400 0 9,830,400 ≤ fVCLK < 19,660,800 1 19,660,800 ≤ fVCLK < 39,321,600 2 NOTE: Do not program E to a value of 3. 8. Select a VCO linear range multiplier, L, where fNOM = 38.4 kHz Freescale Semiconductor, Inc...  f VCLK  L = round  --------------------------  2E × f  NOM 9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Functional Description c. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. d. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L. e. In the PLL reference divider select register (PMDS), program the binary coded equivalent of R.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.4.8 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Functional Description The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the crystal manufacturer’s data for more information regarding values for C1 and C2. Figure 7-2 also shows the external components for the PLL: • Bypass capacitor, CBYP • Filter network Freescale Semiconductor, Inc... Routing should be done with great care to minimize signal cross talk and noise.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.5 I/O Signals The following paragraphs describe the CGMC I/O signals. 7.5.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 7.5.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier. 7.5.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) I/O Signals 7.5.6 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. 7.5.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB) OSCSTOPENB is a bit in the CONFIG register that enables the oscillator to continue operating during stop mode. If this bit is set, the Oscillator continues running during stop mode.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.6 CGMC Registers These registers control and monitor operation of the CGMC: • PLL control register (PCTL) (See PLL Control Register.) • PLL bandwidth control register (PBWC) (See PLL Bandwidth Control Register.) • PLL multiplier select register high (PMSH) (See PLL Multiplier Select Register High.) • PLL multiplier select register low (PMSL) (See PLL Multiplier Select Register Low.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) CGMC Registers $003A $003B Read: PLL VCO Select Range Write: Register (PMRS) Reset: Read: PLL Reference Divider Write: Select Register (PMDS) Reset: VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 0 1 0 0 0 0 0 0 0 0 0 0 RDS3 RDS2 RDS1 RDS0 0 0 0 0 0 0 0 1 = Unimplemented R = Reserved NOTES: 1. When AUTO = 0, PLLIE is forced clear and is read-only. 2.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF — PLL Interrupt Flag Bit Freescale Semiconductor, Inc... This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) CGMC Registers is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See Base Clock Selector Circuit.) PRE1 and PRE0 — Prescaler Program Bits These read/write bits control a prescaler that selects the prescaler power-of-two multiplier, P. (See PLL Circuits and Programming the PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.6.2 PLL Bandwidth Control Register Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) CGMC Registers 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as logic 0s. 7.6.4 PLL Multiplier Select Register Low Freescale Semiconductor, Inc... The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) CGMC Registers 7.6.5 PLL VCO Range Select Register NOTE: PMRS may be called PVRS on other HC08 derivatives. The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: $003A Bit 7 6 5 4 3 2 1 Bit 0 VRS7 VRS6 VRS5 VRS4 VRS3 VRS2 VRS1 VRS0 0 1 0 0 0 0 0 0 Freescale Semiconductor, Inc... Read: Write: Reset: Figure 7-8.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) 7.6.6 PLL Reference Divider Select Register NOTE: PMDS may be called PRDS on other HC08 derivatives. The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider. Address: Freescale Semiconductor, Inc... Read: $003B Bit 7 6 5 4 0 0 0 0 3 2 1 Bit 0 RDS3 RDS2 RDS1 RDS0 0 0 0 1 Write: Reset: 0 0 0 0 = Unimplemented Figure 7-9.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Interrupts 7.7 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Generator Module (CGMC) mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. 7.8.2 Stop Mode If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGMC (oscillator and phase locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT, and CGMINT).
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Acquisition/Lock Time Specifications 7.9 Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 7.9.1 Acquisition/Lock Time Definitions Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Freescale Semiconductor, Inc... The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error.
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Freescale Semiconductor, Inc. Clock Generator Module (CGMC) Acquisition/Lock Time Specifications 7.9.3 Choosing a Filter As described in Parametric Influences on Reaction Time, the external filter network is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. Freescale Semiconductor, Inc... Either of the filter networks in Figure 7-10 is recommended when using a 32.768-kHz reference crystal.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Clock Generator Module (CGMC) Technical Data 128 MC68HC908GR8 — Rev 4.0 Clock Generator Module (CGMC) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 8. Configuration Register (CONFIG) 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 8.2 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Configuration Register (CONFIG) NOTE: To ensure correct operation of the MCU under all operating conditions, the user must write data $1C to address $0033 immediately after reset. This is to ensure proper termination of an unused module within the MCU. NOTE: On a FLASH device, the options except LVI5OR3 are one-time writeable by the user after each reset. The LVI5OR3 bit is one-time writeable by the user only after each POR (power-on reset).
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Freescale Semiconductor, Inc. Configuration Register (CONFIG) Functional Description OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See Clock Generator Module (CGM) subsection Stop Mode.
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Freescale Semiconductor, Inc. Configuration Register (CONFIG) LVI5OR3 — LVI 5V or 3V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module. See Low-Voltage Inhibit (LVI). The voltage mode selected for the LVI should match the operating VDD. See Electrical Specifications for the LVI’s voltage trip points for each of the modes. 1 = LVI operates in 5V mode. 0 = LVI operates in 3V mode. SSREC — Short Stop Recovery Bit Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 9. Computer Operating Properly (COP) 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.5 COP Control Register . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Computer Operating Properly (COP) Freescale Semiconductor, Inc... RESET STATUS REGISTER COP TIMEOUT CLEAR STAGES 5–12 STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH RESET CIRCUIT 12-BIT COP PRESCALER CLEAR ALL STAGES CGMXCLK COPCTL WRITE COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (FROM CONFIG) RESET COPCTL WRITE CLEAR COP COUNTER COP RATE SEL (FROM CONFIG) Figure 9-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Computer Operating Properly (COP) I/O Signals In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held at VTST. During the break state, VTST on the RST pin disables the COP. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly. 9.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Computer Operating Properly (COP) 9.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 9.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Configuration Register (CONFIG). 9.4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Computer Operating Properly (COP) Monitor Mode 9.7 Monitor Mode When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs. 9.8 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Computer Operating Properly (COP) Technical Data 138 MC68HC908GR8 — Rev 4.0 Computer Operating Properly (COP) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 10. Central Processing Unit (CPU) 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.4 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.5 Arithmetic/logic unit (ALU) . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) • 64K byte program/data memory space • 16 addressing modes • Memory-to-memory data moves without using accumulator • Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • Enhanced binary-coded decimal (BCD) data handling • Modular architecture with expandable internal bus definition for extension of addressing range beyond 64K bytes • Low-power stop and wait modes 10.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) CPU registers 10.4.1 Accumulator (A) The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: A Write: Reset: Unaffected by reset Figure 10-2. Accumulator (A) 10.4.2 Index register (H:X) The 16-bit index register allows indexed addressing of a 64K byte memory space.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) 10.4.3 Stack pointer (SP) The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) CPU registers During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Bit 0 1 Read: PC Write: Reset: Loaded with vector from $FFFE and $FFFF Figure 10-5. Program counter (PC) 10.4.
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Freescale Semiconductor, Inc. Central Processing Unit (CPU) The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an ADD or ADC operation. The halfcarry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I — Interrupt mask Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Arithmetic/logic unit (ALU) N — Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) 10.6.1 WAIT mode The WAIT instruction: • clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from WAIT mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. • Disables the CPU clock 10.6.2 STOP mode The STOP instruction: • clears the interrupt mask (I bit) in the condition code register, enabling external interrupts.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary 10.8 Instruction Set Summary Table 10-1 provides a summary of the M68HC08 instruction set.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) V H I N Z C Mn ← 0 Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 10-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) Instruction Set Summary V H I N Z C Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 10-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit (CPU) V H I N Z C NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP Negate (Two’s Complement) NOP No Operation NSA Nibble Swap A 30 dd 40 50 60 ff 70 9E60 ff Cycles Description Operand Operation Effect on CCR Opcode Source Form Address Mode Table 10-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Technical Data Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Central Processing Unit (CPU) Technical Data 156 MC68HC908GR8 — Rev 4.0 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 11. Flash Memory 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.4 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.5 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 160 11.
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Freescale Semiconductor, Inc. Flash Memory Register (FLCR). Details for these operations appear later in this section. The FLASH is organized internally as a 8192-word by 8-bit CMOS page erase, byte (8-bit) program Embedded Flash Memory. Each page consists of 64 bytes. The page erase operation erases all words within a page. A page is composed of two adjacent rows. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash Memory FLASH Control Register 11.4 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations. Address: Read: $FE08 Bit 7 6 5 4 0 0 0 0 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 Write: Freescale Semiconductor, Inc... Reset: 0 0 0 0 Figure 11-1.
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Freescale Semiconductor, Inc. Flash Memory PGM — Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected Freescale Semiconductor, Inc... 11.5 FLASH Page Erase Operation Use this step-by-step procedure to erase a page (64 bytes) of FLASH memory to read as logic 1: 1.
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Freescale Semiconductor, Inc. Flash Memory FLASH Mass Erase Operation 11.6 FLASH Mass Erase Operation Use this step-by-step procedure to erase entire FLASH memory to read as logic 1: 1. Set both the ERASE bit, and the MASS bit in the FLASH control register. 2. Read from the FLASH block protect register. Freescale Semiconductor, Inc... 3. Write any data to any FLASH address* within the FLASH memory address range. 4. Wait for a time, tnvs (min. 10µs) 5. Set the HVEN bit. 6. Wait for a time, tMErase (min.
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Freescale Semiconductor, Inc. Flash Memory 11.7 FLASH Program/Read Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0. Use this step-by-step procedure to program a row of FLASH memory (Figure 112 is a flowchart representation): Freescale Semiconductor, Inc... 1. Set the PGM bit.
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Freescale Semiconductor, Inc. Flash Memory FLASH Block Protection NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed tPROG maximum. See Memory Characteristics. 11.8 FLASH Block Protection Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash Memory 1 Algorithm for programming a row (32 bytes) of FLASH memory 2 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Flash Memory FLASH Block Protection 11.8.1 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash Memory Examples of protect start address: Table 11-1. Examples of protect start address: BPR[7:0] Start of Address of Protect Range $80 The entire FLASH memory is protected. $81 (1000 0001) $E040 (1110 0000 0100 0000) $82 (1000 0010) $E080 (1110 0000 1000 0000) and so on... $FE (1111 1110) $FF80 (1111 1111 1000 0000) $FF The entire FLASH memory is not protected. Note: The end address of the protected range is always $FFFF. 11.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 12. External Interrupt (IRQ) 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 12.5 IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. External Interrupt (IRQ) 12.4 Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 12-1 shows the structure of the IRQ module. Freescale Semiconductor, Inc... Interrupt signals on the IRQ1 pin are latched into the IRQ latch.
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External Interrupt (IRQ) Functional Description NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. ACK RESET INTERNAL ADDRESS BUS Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. TO CPU FOR BIL/BIH INSTRUCTIONS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE VDD IRQF D IRQ1 CLR Q SYNCHRONIZER CK IRQ INTERRUPT REQUEST IRQ FF IMASK MODE TO MODE SELECT LOGIC HIGH VOLTAGE DETECT Figure 12-1.
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Freescale Semiconductor, Inc. External Interrupt (IRQ) 12.5 IRQ1 Pin A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. Freescale Semiconductor, Inc... If the MODE bit is set, the IRQ1 pin is both falling-edge-sensitive and low-level-sensitive.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. External Interrupt (IRQ) IRQ Module During Break Interrupts The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
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Freescale Semiconductor, Inc. External Interrupt (IRQ) 12.7 IRQ Status and Control Register Freescale Semiconductor, Inc... The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module.
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Freescale Semiconductor, Inc. External Interrupt (IRQ) IRQ Status and Control Register MODE — IRQ Edge/Level Select Bit Freescale Semiconductor, Inc... This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE. 1 = IRQ1 interrupt requests on falling edges and low levels 0 = IRQ1 interrupt requests on falling edges only MC68HC908GR8 — Rev 4.0 MOTOROLA Technical Data External Interrupt (IRQ) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... External Interrupt (IRQ) Technical Data 174 MC68HC908GR8 — Rev 4.0 External Interrupt (IRQ) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 13. Keyboard Interrupt (KBI) 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.5 Keyboard Initialization. . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) 13.4 Functional Description Writing to the KBIE3–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) Functional Description INTERNAL BUS KBD0 ACKK VDD VECTOR FETCH DECODER KEYF RESET . TO PULLUP ENABLE D CLR Q SYNCHRONIZER . CK KB0IE KEYBOARD INTERRUPT REQUEST . KEYBOARD INTERRUPT FF KBD3 IMASKK MODEK TO PULLUP ENABLE KB3IE Figure 13-1. Keyboard Module Block Diagram Addr.
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Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) Freescale Semiconductor, Inc... If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the interrupt request.
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Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) Keyboard Initialization NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. 13.5 Keyboard Initialization Freescale Semiconductor, Inc... When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) 13.6 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 13.6.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 13.6.2 Stop Mode The keyboard module remains active in stop mode.
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Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) I/O Registers 13.8 I/O Registers These registers control and monitor operation of the keyboard module: • Keyboard status and control register (INTKBSCR) • Keyboard interrupt enable register (INTKBIER) 13.8.1 Keyboard Status and Control Register Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Keyboard Interrupt (KBI) ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 14. Low-Voltage Inhibit (LVI) 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 14.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) 14.4 Functional Description Freescale Semiconductor, Inc... Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below the trip point voltage, VTRIPF.
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Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) Functional Description LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (MOR1). See Configuration Register (CONFIG) for details of the LVI’s configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) Addr. $FE0C Register Name Bit 7 Read: LVIOUT LVI Status Register Write: (LVISR) Reset: 0 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = Unimplemented Figure 14-2. LVI I/O Register Summary 14.4.1 Polled LVI Operation In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) LVI Status Register 14.4.4 LVI Trip Selection The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5V or 3V protection. NOTE: The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this. (See Electrical Specifications for the actual trip point voltages.) 14.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Low-Voltage Inhibit (LVI) 14.6 LVI Interrupts The LVI module does not generate interrupt requests. 14.7 Low-Power Modes The STOP and WAIT instructions put the MCU in low powerconsumption standby modes. 14.7.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 14.7.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 15. Monitor ROM (MON) 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 15.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Monitor ROM (MON) • FLASH memory security feature(1) • FLASH memory programming interface • Enhanced PLL (phase-locked loop) option to allow use of external 32.768-kHz crystal to generate internal frequency of 2.
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Monitor ROM (MON) Functional Description 68HC08 RST 0.1 µF VTST (SEE NOTE 3) RESET VECTORS $FFFE 10 kΩ (SEE NOTES 2 SW2 AND 3) C VDDA D $FFFF IRQ VDDA 0.033 µF SW3 (SEE NOTE 2) C 1 10 µF + MC145407 3 6–30 pF 20 + 10 µF 18 D C 32.768 kHz XTAL 4 10 µF 17 330 kΩ + + 2 19 DB-25 2 5 16 3 6 15 10 µF VDD 0.01 µF CGMXFC 10 k 10 MΩ Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Monitor ROM (MON) The monitor code has been updated from previous versions to allow enabling the PLL to generate the internal clock, provided the reset vector is blank, when the device is being clocked by a low-frequency crystal. This addition, which is enabled when IRQ is held low out of rest, is intended to support serial communication/ programming at 9600 baud in monitor mode by stepping up the external frequency (assumed to be 32.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description Table 15-1. Monitor Mode Signal Requirements and Options IRQ RESET $FFFE/ $FFFF X GND X VTST VDD or VTST X VDD VDD $FFFF GND VDD $FFFF PLL PTB0 PTB1 X X OFF 1 OFF X ON Bus Freq COP 0 Disabled X X 0 0 9.8304 MHz 4.9152 MHz 2.4576 Disabled MHz 9.8304 MHz 4.9152 MHz 2.4576 Disabled MHz 32.768 kHz 4.9152 MHz 2.
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Freescale Semiconductor, Inc. Monitor ROM (MON) requirements and conditions, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. NOTE: If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial POR reset. Once the part has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description POR RESET IS VECTOR BLANK? NO NORMAL USER MODE YES MONITOR MODE Freescale Semiconductor, Inc... EXECUTE MONITOR CODE POR TRIGGERED? NO YES Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with pin configuration shown in Figure 15-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Monitor ROM (MON) Table 15-2 summarizes the differences between user mode and monitor mode. Table 15-2. Mode Differences Functions Modes Reset Vector High Reset Vector Low Break Vector High Break Vector Low SWI Vector High SWI Vector Low User $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD Monitor $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD 15.4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description 15.4.4 Baud Rate The communication baud rate is controlled by the crystal frequency upon entry into monitor mode. The divide by ratio is 1024. If monitor mode was entered with VDD on IRQ, then the divide by ratio is also set at 1024. If monitor mode was entered with VSS on IRQ, then the internal PLL steps up the external frequency, presumed to be 32.768 kHz, to 2.4576 MHz.
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Freescale Semiconductor, Inc. Monitor ROM (MON) The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE: Wait one bit time after each echo before sending the next byte.
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Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description A brief description of each monitor mode command is given in Table 154 through Table 15-9. Table 15-4. READ (Read Memory) Command Description Operand 2-byte address in high-byte:low-byte order Data Returned Returns contents of specified address Opcode Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Monitor ROM (MON) Table 15-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Freescale Semiconductor, Inc... Command Sequence FROM HOST IREAD IREAD DATA ECHO DATA RETURN Table 15-7.
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Freescale Semiconductor, Inc. Monitor ROM (MON) Functional Description A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64K byte memory map. Table 15-8. READSP (Read Stack Pointer) Command Description Operand None Data Returned Returns incremented stack pointer value (SP + 1) in high-byte:lowbyte order Opcode Freescale Semiconductor, Inc... Reads stack pointer $0C Command Sequence FROM HOST READSP SP HIGH READSP ECHO SP LOW RETURN Table 15-9.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Monitor ROM (MON) The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
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Freescale Semiconductor, Inc. Monitor ROM (MON) Security VDD 4096 + 32 CGMXCLK CYCLES RST 24 BUS CYCLES COMMAND PA1 BYTE 8 BYTE 2 BYTE 1 256 BUS CYCLES (MINIMUM) Freescale Semiconductor, Inc... FROM HOST PA0 4 BREAK 2 NOTES: 1 = Echo delay, 2 bit times 2 = Data return delay, 2 bit times 4 = Wait 1 bit time before sending next byte. 1 COMMAND ECHO 1 BYTE 8 ECHO BYTE 1 ECHO FROM MCU 1 BYTE 2 ECHO 4 1 Figure 15-8.
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Freescale Semiconductor, Inc. Monitor ROM (MON) Freescale Semiconductor, Inc... If the security sequence fails, the device can be reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH mode can also be bulk erased by executing an erase routine that was downloaded into internal RAM. The bulk erase operation clears the security code locations so that all eight security bytes become $FF (blank). Technical Data 204 MC68HC908GR8 — Rev 4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 16. Input/Output Ports (I/O) 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 16.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 16.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.5 Port C . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Input/Output Ports (I/O) Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Input/Output Ports (I/O) Introduction Addr.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) Table 16-1. Port Control Register Bits Summary Port Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port A 16.3 Port A Port A is an 4-bit special-function port that shares all four of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port. 16.3.1 Port A Data Register Freescale Semiconductor, Inc... The port A data register (PTA) contains a data latch for each of the four port A pins.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) 16.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer. Address: Freescale Semiconductor, Inc... Read: $0004 Bit 7 6 5 4 0 0 0 0 3 2 1 Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 Write: Reset: 0 0 0 0 Figure 16-3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port A READ DDRA ($0004) INTERNAL DATA BUS WRITE DDRA ($0004) DDRAx RESET WRITE PTA ($0000) PTAx PTAx VDD PTAPUEx READ PTA ($0000) INTERNAL PULLUP DEVICE Figure 16-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) 16.3.3 Port A Input Pullup Enable Register The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each of the four port A pins. Each bit is individually configurable and requires that the data direction register, DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRA is configured for output mode. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port B 16.4 Port B Port B is an 6-bit special-function port that shares all six of its pins with the analog-to-digital converter (ADC) module. 16.4.1 Port B Data Register Freescale Semiconductor, Inc... The port B data register (PTB) contains a data latch for each of the six port pins.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) 16.4.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer. Address: Freescale Semiconductor, Inc... Read: $0005 Bit 7 6 0 0 5 4 3 2 1 Bit 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 Write: Reset: 0 0 Figure 16-7.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port B INTERNAL DATA BUS READ DDRB ($0005) WRITE DDRB ($0005) RESET DDRBx WRITE PTB ($0001) PTBx PTBx READ PTB ($0001) Figure 16-8. Port B I/O Circuit When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) 16.5 Port C Port C is a 2-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 16.5.1 Port C Data Register Freescale Semiconductor, Inc... The port C data register (PTC) contains a data latch for each of the two port C pins. Address: Read: $0002 Bit 7 6 5 4 3 2 0 0 0 0 0 0 1 Bit 0 PTC1 PTC0 Write: Reset: Unaffected by reset = Unimplemented Figure 16-9.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port C 16.5.2 Data Direction Register C Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer. Freescale Semiconductor, Inc... Address: Read: $0006 Bit 7 6 5 4 3 2 0 0 0 0 0 0 1 Bit 0 DDRC1 DDRC0 0 0 Write: Reset: 0 0 0 0 0 0 = Unimplemented Figure 16-10.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Input/Output Ports (I/O) READ DDRC ($0006) INTERNAL DATA BUS WRITE DDRC ($0006) DDRCx RESET WRITE PTC ($0002) PTCx PTCx VDD PTCPUEx READ PTC ($0002) INTERNAL PULLUP DEVICE Figure 16-11. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port C 16.5.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the two port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRC is configured for output mode. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) 16.6 Port D Port D is an 7-bit special-function port that shares four of its pins with the serial peripheral interface (SPI) module and three of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software configurable pullup devices if configured as an input port. 16.6.1 Port D Data Register Freescale Semiconductor, Inc... The port D data register (PTD) contains a data latch for each of the seven port D pins. .
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port D T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD5/T1CH1–PTD4/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD5/T1CH1–PTD4/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Timer Interface Module (TIM). SPSCK — SPI Serial Clock Freescale Semiconductor, Inc... The PTD3/SPSCK pin is the serial clock input of the SPI module.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) 16.6.2 Data Direction Register D Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. Address: $0007 Freescale Semiconductor, Inc... Bit 7 Read: 6 5 4 3 2 1 Bit 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 Write: Reset: 0 Figure 16-14.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port D READ DDRD ($0007) INTERNAL DATA BUS WRITE DDRD ($0007) DDRDx RESET WRITE PTD ($0003) PTDx PTDx VDD PTDPUEx READ PTD ($0003) INTERNAL PULLUP DEVICE Figure 16-15. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) 16.6.3 Port D Input Pullup Enable Register The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the seven port D pins. Each bit is individually configurable and requires that the data direction register, DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRD is configured for output mode. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port E 16.7 Port E Port E is a 2-bit special-function port that shares two of its pins with the serial communications interface (SCI) module. 16.7.1 Port E Data Register Freescale Semiconductor, Inc... The port E data register contains a data latch for each of the two port E pins.
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Freescale Semiconductor, Inc. Input/Output Ports (I/O) TxD — SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See Serial Communications Interface (SCI). 16.7.2 Data Direction Register E Freescale Semiconductor, Inc... Data direction register E (DDRE) determines whether each port E pin is an input or an output.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Input/Output Ports (I/O) Port E INTERNAL DATA BUS READ DDRE ($000C) WRITE DDRE ($000C) RESET DDREx WRITE PTE ($0008) PTEx PTEx READ PTE ($0008) Figure 16-19. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Input/Output Ports (I/O) Technical Data 228 MC68HC908GR8 — Rev 4.0 Input/Output Ports (I/O) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 17. RAM 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 17.2 Introduction This section describes the 384 bytes of RAM (random-access memory). 17.3 Functional Description Addresses $0040 through $01BF are RAM locations.
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Freescale Semiconductor, Inc. RAM During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. Freescale Semiconductor, Inc... NOTE: Technical Data 230 MC68HC908GR8 — Rev 4.0 RAM For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 18. Serial Communications Interface (SCI) 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 18.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 18.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 18.5 Functional Description . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 18.3 Features Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Pin Name Conventions 18.4 Pin Name Conventions The generic names of the SCI I/O pins are: • RxD (receive data) • TxD (transmit data) SCI I/O (input/output) lines are implemented by sharing parallel I/O port pins. The full name of an SCI input or output reflects the name of the shared port pin. Table 18-1 shows the full names and the generic names of the SCI I/O pins.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 18.5.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 18-3.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description SCIBDSRC FROM CONFIG2 SL A CGMXCLK X B IT12 SL = 0 => X = A SL = 1 => X = B INTERNAL BUS BAUD DIVIDER ÷ 16 SCI DATA REGISTER 11-BIT TRANSMIT SHIFT REGISTER STOP Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 18.5.2.2 Character Transmission During an SCI transmission, the transmit shift register shifts a character out to the PE2/TxD pin. The SCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register. To initiate an SCI transmission: 1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1). Freescale Semiconductor, Inc... 2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 18.5.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. See SCI Control Register 1. 18.5.2.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description 18.5.3.2 Character Reception During an SCI reception, the receive shift register shifts characters in from the PE1/RxD pin. The SCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register. Freescale Semiconductor, Inc... After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) INTERNAL BUS SCIBDSRC FROM CONFIG2 SCR1 SCR0 PRESCALER BAUD DIVIDER ÷ 16 DATA RECOVERY PE1/RxD Freescale Semiconductor, Inc...
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Serial Communications Interface (SCI) Functional Description 18.5.3.3 Data Sampling The receiver samples the PE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... Table 18-2. Start Bit Verification RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag 000 Yes 0 001 Yes 1 010 Yes 1 011 No 0 100 Yes 1 101 No 0 110 No 0 111 No 0 Start bit verification is not successful if any two of the three verification samples are logic 1s. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description NOTE: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. 18.5.3.
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Serial Communications Interface (SCI) Functional Description With the misaligned character shown in Figure 18-7, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is 170 – 163 × 100 = 4.12% -------------------------170 18.5.3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 18-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Functional Description SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle may cause the receiver to wake up immediately. 18.5.3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) • Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. • Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCI During Break Module Interrupts 18.7 SCI During Break Module Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 18.8.2 PE1/RxD (Receive Data) The PE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PE1/RxD pin with port E. When the SCI is enabled, the PE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). 18.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers Address: $0013 Bit 7 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 Read: Write: Reset: Freescale Semiconductor, Inc... Figure 18-9. SCI Control Register 1 (SCC1) LOOPS — Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the PE1/RxD pin is disconnected from the SCI, and the transmitter output goes into the receiver input.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 1 = 9-bit SCI characters 0 = 8-bit SCI characters WAKE — Wakeup Condition Bit Freescale Semiconductor, Inc... This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the PE1/RxD pin. Reset clears the WAKE bit.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers NOTE: Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Table 18-5.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Address: $0014 Bit 7 6 5 4 3 2 1 Bit 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 0 0 0 0 0 0 0 Read: Write: Reset: Freescale Semiconductor, Inc... Figure 18-10. SCI Control Register 2 (SCC2) SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Reset clears the SCTIE bit.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1. RE — Receiver Enable Bit Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 18.9.3 SCI Control Register 3 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers DMARE — DMA Receive Enable Bit CAUTION: The DMA module is not included on this MCU. Writing a logic 1 to DMARE or DMATE may adversely affect MCU performance.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) PEIE — Receiver Parity Error Interrupt Enable Bit This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. See SCI Status Register 1. Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled Freescale Semiconductor, Inc... 18.9.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC — Transmission Complete Bit Freescale Semiconductor, Inc... This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) OR — Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 18.9.5 SCI Status Register 2 SCI status register 2 contains flags to signal the following conditions: • Break character detected • Incoming data Address: $0017 Bit 7 6 5 4 3 2 Read: 1 Bit 0 BKF RPF 0 0 Freescale Semiconductor, Inc... Write: Reset: 0 0 0 0 0 0 = Unimplemented Figure 18-14.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers 18.9.6 SCI Data Register The SCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register. Address: $0018 Bit 7 6 5 4 3 2 1 Bit 0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by reset Figure 18-15.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in Table 18-6. Reset clears SCP1 and SCP0. Freescale Semiconductor, Inc... Table 18-6. SCI Baud Rate Prescaling SCP1 and SCP0 Prescaler Divisor (PD) 00 1 01 3 10 4 11 13 SCR2–SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 18-7. Reset clears SCR2–SCR0.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) I/O Registers Use this formula to calculate the SCI baud rate: f BUS baud rate = -----------------------------------64 × PD × BD where: fBUS = bus frequency PD = prescaler divisor BD = baud rate divisor Freescale Semiconductor, Inc... SCI_BDSRC is an input to the SCI. Normally it will be tied off low at the top level to select the bus clock as the clock source.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... Table 18-8. SCI Baud Rate Selection Examples SCP1 and SCP0 Prescaler Divisor (PD) SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) Baud Rate (fBUS = 4.
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Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Freescale Semiconductor, Inc... Table 18-8. SCI Baud Rate Selection Examples SCP1 and SCP0 Prescaler Divisor (PD) SCR2, SCR1, and SCR0 Baud Rate Divisor (BD) Baud Rate (fBUS = 4.9152 MHz) 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 Technical Data 269 MC68HC908GR8 — Rev 4.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Serial Communications Interface (SCI) Technical Data 270 MC68HC908GR8 — Rev 4.0 Serial Communications Interface (SCI) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 19. System Integration Module (SIM) 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 19.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 275 19.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 276 19.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) – Vector address generation • CPU enable/disable timing • Modular architecture expandable to 128 interrupt sources Table 19-1 shows the internal signal names used in this section.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) Introduction Table 19-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) Addr. Register Name Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Bit 7 6 5 4 3 2 R R R R R R 1 Bit 0 SBSW R NOTE 0 0 0 0 0 0 0 0 POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 R R R R R R R R BCFE R R R R R R R Note: Writing a logic 0 clears SBSW.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) SIM Bus Clock Control and Generation 19.3 SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 19-3. This clock can come from either an external oscillator or from the on-chip PLL. See Clock Generator Module (CGMC).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) 19.3.2 Clock Startup from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout. 19.3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) Reset and System Initialization An internal reset clears the SIM counter (see SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See SIM Registers. 19.4.1 External Pin Reset The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all processing.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) then follows the sequence from the falling edge of RST shown in Figure 19-5. IRST RST RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES CGMXCLK IAB VECTOR HIGH Figure 19-5. Internal Reset Timing The COP reset is asynchronous to the bus clock. ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR INTERNAL RESET Figure 19-6.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) Reset and System Initialization • The internal reset signal is asserted. • The SIM enables CGMOUT. • Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. • The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) The COP module is disabled if the RST pin or the IRQ pin is held at Vtst while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, Vtst on the RST pin disables the COP module. 19.4.2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) SIM Counter 19.4.2.6 Monitor Mode Entry Module Reset (MODRST) The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are blank ($00). (See Entering Monitor Mode.) When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources. 19.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) 19.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See Stop Mode for details.) The SIM counter is free-running after all reset states. (See Active Resets from Internal Sources for counter control and internal reset recovery sequences.) 19.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) Exception Control MODULE INTERRUPT I BIT IAB IDB SP DUMMY DUMMY SP – 1 PC – 1[7:0] SP – 2 PC–1[15:8] SP – 3 X SP – 4 A VECT H CCR VECT L V DATA H START ADDR V DATA L OPCODE R/W Figure 19-8. Interrupt Entry Timing MODULE INTERRUPT I BIT IAB SP – 4 IDB SP – 3 CCR SP – 2 A SP – 1 X SP PC – 1 [7:0] PC PC–1[15:8] PC + 1 OPCODE OPERAND R/W Figure 19-9.
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Freescale Semiconductor, Inc. System Integration Module (SIM) FROM RESET BREAK I BIT SET? INTERRUPT? YES NO YES I BIT SET? Freescale Semiconductor, Inc... NO IRQ0 INTERRUPT? YES NO IRQ INTERRUPT? NO AS MANY INTERRUPTS AS EXIST ON CHIP YES STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR FETCH NEXT INSTRUCTION SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES UNSTACK CPU REGISTERS NO EXECUTE INSTRUCTION Figure 19-10. Interrupt Processing 19.6.1.
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Freescale Semiconductor, Inc. System Integration Module (SIM) Exception Control condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Freescale Semiconductor, Inc... If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 19-11 demonstrates what happens when two interrupts are pending.
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Freescale Semiconductor, Inc. System Integration Module (SIM) 19.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does. Freescale Semiconductor, Inc... 19.6.1.
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Freescale Semiconductor, Inc. System Integration Module (SIM) Exception Control Table 19-3. Interrupt Sources Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) 19.6.1.4 Interrupt Status Register 1 Address: $FE04 Bit 7 6 5 4 3 2 1 Bit 0 Read: I6 I5 I4 I3 I2 I1 0 0 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 19-12. Interrupt Status Register 1 (INT1) I6–I1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt requests from the sources shown in Table 19-3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) Exception Control 19.6.1.6 Interrupt Status Register 3 Address: $FE06 Bit 7 6 5 4 3 2 1 Bit 0 Read: 0 0 0 0 0 0 I16 I15 Write: R R R R R R R R Reset: 0 0 0 0 0 0 0 0 R = Reserved Figure 19-14.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) 19.6.4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode.
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Freescale Semiconductor, Inc. System Integration Module (SIM) Low-Power Modes wait mode. Some modules can be programmed to be active in wait mode. Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) 32 CYCLES IAB IDB 32 CYCLES $6E0B $A6 $A6 RST VCT H RST VCT L $A6 RST CGMXCLK Figure 19-17. Wait Recovery from Internal Reset 19.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) SIM Registers CPUSTOP IAB IDB STOP ADDR STOP ADDR + 1 PREVIOUS DATA SAME NEXT OPCODE SAME SAME SAME R/W Note : Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 19-18. Stop Mode Entry Timing STOP RECOVERY PERIOD CGMXCLK INT/BREAK IAB STOP +1 STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3 Figure 19-19. Stop Mode Recovery from Interrupt or Break 19.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. System Integration Module (SIM) 19.8.1 SIM Break Status Register The SIM break status register (SBSR) contains a flag to indicate that a break caused an exit from stop mode or wait mode. Address: $FE00 Bit 7 6 5 4 3 2 R R R R R R 0 0 0 0 0 0 Read: Bit 0 SBSW Write: Reset: 1 R Note(1) 0 R 0 = Reserved Note: 1. Writing a logic 0 clears SBSW. Figure 19-20.
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Freescale Semiconductor, Inc. System Integration Module (SIM) DEC HIBYTE,SP ;Else deal with high byte, too. DOLO DEC LOBYTE,SP ;Point to WAIT/STOP opcode. RETURN PULH RTI ;Restore H register. 19.8.2 SIM Reset Status Register Freescale Semiconductor, Inc... This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 20. Serial Peripheral Interface (SPI) Freescale Semiconductor, Inc... 20.1 Contents 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 20.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 20.4 Pin Name Conventions and I/O Register Addresses . . . . . . . 298 20.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 20.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description The full names of the SPI I/O pins are shown in Table 20-1. The generic pin names appear in the text that follows. Table 20-1. Pin Name Conventions SPI Generic Pin Names: Full SPI Pin Names: SPI MISO MOSI SS SPSCK CGND PTD1/ATD9 PTD2/ATD1 0 PTD0/AT D8 PTD3/ATD11 VSS 20.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) INTERNAL BUS TRANSMIT DATA REGISTER CGMOUT ÷ 2 FROM SIM SHIFT REGISTER 7 6 5 4 3 2 1 MISO 0 ÷2 MOSI ÷8 CLOCK DIVIDER ÷ 32 RECEIVE DATA REGISTER PIN CONTROL LOGIC Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Functional Description The following paragraphs describe the operation of the SPI module. 20.5.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. Freescale Semiconductor, Inc... NOTE: Configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See SPI Control Register.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. See SPI Status and Control Register. Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s MISO pin.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Transmission Formats When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Transmission Formats SPSCK CYCLE # FOR REFERENCE 1 2 3 4 5 6 7 8 MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE MSB SS; TO SLAVE Freescale Semiconductor, Inc... CAPTURE STROBE Figure 20-4. Transmission Format (CPHA = 0) MISO/MOSI BYTE 1 BYTE 2 BYTE 3 MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 Figure 20-5.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Freescale Semiconductor, Inc... out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Transmission Formats When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) WRITE TO SPDR INITIATION DELAY BUS CLOCK MOSI MSB BIT 6 1 2 BIT 5 SPSCK CPHA = 1 SPSCK CPHA = 0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Queuing Transmission Data 20.7 Queuing Transmission Data Freescale Semiconductor, Inc... The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Error Conditions interrupts share the same CPU interrupt vector. See Figure 20-11. It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. Freescale Semiconductor, Inc... If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 20-9 shows how it is possible to miss an overflow.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) BYTE 1 SPI RECEIVE COMPLETE BYTE 2 5 1 BYTE 3 7 BYTE 4 11 SPRF OVRF READ SPSCR 2 READ SPDR 4 3 1 BYTE 1 SETS SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 3 6 9 8 12 14 10 13 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 9 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. 10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Error Conditions MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. See Figure 20-11. It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Interrupts Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register. The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1). Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) The following sources in the SPI status and control register can generate CPU interrupt requests: • SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) Low-Power Modes By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set. 20.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 20.12 SPI During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See System Integration Module (SIM). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Signals communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD. 20.13.1 MISO (Master In/Slave Out) MISO is one of the two SPI module pins that transmits serial data.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 20.13.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Signals When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. See Mode Fault Error. For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 20.14 I/O Registers Three registers control and monitor SPI operation: • SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR) Freescale Semiconductor, Inc... 20.14.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers SPRIE — SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled DMAS —DMA Select Bit Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) SPE — SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See Resetting the SPI. Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE— SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers Address: $0011 Bit 7 Read: 6 SPRF 5 4 3 OVRF MODF SPTE ERRIE 2 1 Bit 0 MODFEN SPR1 SPR0 0 0 0 Write: Reset: 0 0 0 0 1 = Unimplemented Freescale Semiconductor, Inc... Figure 20-14. SPI Status and Control Register (SPSCR) SPRF — SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) MODF — Mode Fault Bit Freescale Semiconductor, Inc... This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) I/O Registers SPR1 and SPR0 — SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 20-4. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Freescale Semiconductor, Inc... Table 20-4.
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Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 20.14.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. See Figure 20-2. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 21. Timebase Module (TBM) 21.1 Contents 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 21.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 21.5 Timebase Register Description. . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Timebase Module (TBM) 21.4 Functional Description NOTE: This module is designed for a 32.768 kHz oscillator. Freescale Semiconductor, Inc... This module can generate a periodic interrupt by dividing the crystal frequency, CGMXCLK. The counter is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 21-1, starts counting when the TBON bit is set. When the counter overflows at the tap selected by TBR2:TBR0, the TBIF bit gets set.
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Freescale Semiconductor, Inc. Timebase Module (TBM) Timebase Register Description 21.5 Timebase Register Description The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the rate. Address: $001C Bit 7 Read: 6 5 4 TBR2 TBR1 TBR0 TBIF Freescale Semiconductor, Inc... 2 1 Bit 0 TBIE TBON Reserved 0 0 0 0 Write: Reset: 3 TACK 0 0 0 0 0 = Unimplemented Figure 21-2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timebase Module (TBM) NOTE: Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1). TACK— Timebase ACKnowledge The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic 0 to this bit has no effect.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timebase Module (TBM) Low-Power Modes 21.7 Low-Power Modes The WAIT and STOP instructions put the MCU in low powerconsumption standby modes. 21.7.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Timebase Module (TBM) Technical Data 334 MC68HC908GR8 — Rev 4.0 Timebase Module (TBM) For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 22. Timer Interface Module (TIM) 22.1 Contents 22.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 22.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 22.4 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 22.5 Functional Description . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) 22.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) Functional Description NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 will refer to T1CH1. NOTE: The Timer Interface Module in MC68HC908GR8 is constructed by TIM1 which is contained channel 0 and 1, and TIM2 which is contained channel 0 only. Freescale Semiconductor, Inc... 22.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) INTERNAL TCLK PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP PS2 TRST PS1 PS0 16-BIT COUNTER TOF TOIE INTERRUPT LOGIC 16-BIT COMPARATOR Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) Functional Description Figure 22-2 summarizes the timer registers. Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) Addr.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) Functional Description 22.5.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. 22.5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) • When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) Functional Description 22.5.6 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 22.5.7 Unbuffered PWM Signal Generation Freescale Semiconductor, Inc... Any output compare channel can generate unbuffered PWM pulses as described in Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) Functional Description 22.5.8 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 22-3. b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 22-3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) Low-Power Modes • TIM overflow flag (TOF) — The TOF bit is set when the TIM counter value reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) 22.8 TIM During Break Interrupts A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM Break Flag Control Register.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) I/O Registers 22.10 I/O Registers NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) TOF — TIM Overflow Flag Bit Freescale Semiconductor, Inc... This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) I/O Registers PS2–PS0 — Prescaler Select Bits These read/write bits select either the TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as Table 22-2 shows. Reset clears the PS[2:0] bits. Freescale Semiconductor, Inc... Table 22-2.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) 22.10.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) I/O Registers 22.10.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) 22.10.4 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) I/O Registers 22.10.5 TIM Channel Status and Control Registers Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) CHxF — Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) I/O Registers 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. See Table 22-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) Table 22-3. Mode, Edge, and Level Selection MSxB:MSxA ELSxB:ELSxA X0 00 Mode Configuration Pin under port control; initial output level high Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Timer Interface Module (TIM) I/O Registers CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As . CHxMAX Latency shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
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Freescale Semiconductor, Inc. Timer Interface Module (TIM) Address: T1CH0H, $0026 and T2CH0H, $0031 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Read: Write: Reset: Indeterminate after reset Freescale Semiconductor, Inc... Figure 22-14. TIM Channel 0 Register High (TCH0H) Address: T1CH0L, $0027 and T2CH0L $0032 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Indeterminate after reset Figure 22-15.
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Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 23. Electrical Specifications Freescale Semiconductor, Inc... 23.1 Contents 23.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362 23.3 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 363 23.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 23.5 5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 364 23.
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Freescale Semiconductor, Inc. Electrical Specifications 23.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly beyond the maximum ratings. Refer to 5.0 V DC Electrical Characteristics for guaranteed operating conditions. Freescale Semiconductor, Inc... Table 23-1. Absolute Maximum Ratings Characteristic(1) Symbol Value Unit Supply voltage VDD –0.3 to + 5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Functional Operating Range 23.3 Functional Operating Range Table 23-2. Functional Operation Range Characteristic Operating temperature range Operating voltage range NOTE: Symbol Value Unit TA –40 to +125 °C VDD 3.0 ±10% 5.0 ±10% V To ensure correct operation of the MCU under all operating conditions, the user must write data $1C to address $0033 immediately after reset.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 23.5 5.0 V DC Electrical Characteristics Table 23-4. 5.0V DC Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.8 VDD – 1.5 VDD – 0.8 — — — — — — — — 50 V V V mA IOH2 — — 50 mA IOHT — — 100 mA VOL VOL VOL IOL1 — — — — — — — — 0.4 1.5 1.0 50 V V V mA IOL2 — — 50 mA IOLT — — 100 mA Input high voltage All ports, IRQs, RESET OSC1 VIH 0.7 x VDD 0.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 5.0 V DC Electrical Characteristics Table 23-4. 5.0V DC Electrical Characteristics Symbol Min Typ(2) Max Unit Pullup resistors (as input only) Ports PTA3/KBD3–PTA0/KBD0, PTC1–PTC0, PTD6/T2CH0–PTD0/SS RPU 20 45 65 kΩ Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD +2.5 — 8 V Low-voltage inhibit, trip falling voltage – target VTRIPF 3.85 4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 23.6 3.0 V DC Electrical Characteristics Table 23-5. 3.0 V DC Electrical Characteristics Symbol Min Typ(2) Max Unit VOH VOH VOH IOH1 VDD – 0.3 VDD – 1.0 VDD – 0.5 — — — — — — — — 30 V V V mA IOH2 — — 30 mA IOHT — — 60 mA VOL VOL VOL IOL1 — — — — — — — — 0.3 1.0 0.8 30 V V V mA IOL2 — — 30 mA IOLT — — 60 mA Input high voltage All ports, IRQs, RESET OSC1 VIH 0.7 x VDD 0.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 3.0 V DC Electrical Characteristics Table 23-5. 3.0 V DC Electrical Characteristics Symbol Min Typ(2) Max Unit Pullup resistors (as input only) Ports PTA3/KBD37–PTA0/KBD0, PTC1–PTC0, PTD6/T2CH0–PTD0/SS RPU 20 45 65 kΩ Capacitance Ports (as input or output) COut CIn — — — — 12 8 pF Monitor mode entry voltage VTST VDD +2.5 — 8 V Low-voltage inhibit, trip falling voltage – target VTRIPF 2.35 2.
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Freescale Semiconductor, Inc. Electrical Specifications 23.7 5.0 V Control Timing Table 23-6. 5.0 V Control Timing Freescale Semiconductor, Inc... Characteristic(1) Symbol Min Max Unit Frequency of operation(2) Crystal option External clock option(3) fosc 32 dc(4) 100 32.8 kHz MHz Internal operating frequency fop — 8.
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Freescale Semiconductor, Inc. Electrical Specifications 3.0 V Control Timing 23.8 3.0 V Control Timing Table 23-7. 3.0 V Control Timing Freescale Semiconductor, Inc... Characteristic(1) Symbol Min Max Unit Frequency of operation(2) Crystal option External clock option(3) fosc 32 dc(4) 100 16.4 kHz MHz Internal operating frequency fop — 4.
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Freescale Semiconductor, Inc. Electrical Specifications 23.9 Output High-Voltage Characteristics 0 –5 IOH (mA) –10 –40 0 25 85 –15 –20 –25 –30 Freescale Semiconductor, Inc... –35 –40 3 3.2 3.4 3.6 VOH (V) 3.8 4.0 4.2 VOH > VDD –0.8 V @ IOH = –2.0 mA VOH > VDD –1.5 V @ IOH = –10.0 mA Figure 23-1. Typical High-Side Driver Characteristics – Port PTA3–PTA0 (VDD = 4.5 Vdc) 0 IOH (mA) –5 –40 0 25 85 –10 –15 –20 –25 1.3 1.5 1.7 1.9 VOH (V) 2.1 2.3 2.5 VOH > VDD –0.3 V @ IOH = –0.
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Freescale Semiconductor, Inc. Electrical Specifications Output High-Voltage Characteristics 0 –5 IOH (mA) –10 –40 0 25 85 –15 –20 –25 –30 –35 –40 Freescale Semiconductor, Inc... 3 3.2 3.4 3.6 VOH (V) 3.8 4.0 4.2 VOH > VDD –0.8 V @ IOH = –10.0 mA Figure 23-3. Typical High-Side Driver Characteristics – Port PTC1–PTC0 (VDD = 4.5 Vdc) 0 IOH (mA) –5 –40 0 25 85 –10 –15 –20 –25 1.3 1.5 1.7 1.9 VOH (V) 2.1 2.3 2.5 VOH > VDD –0.5 V @ IOH = –4.0 mA Figure 23-4.
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Freescale Semiconductor, Inc. Electrical Specifications 0 –10 –20 –40 0 25 85 IOH (mA) –30 –40 –50 –60 –70 –80 –90 Freescale Semiconductor, Inc... 3 3.2 3.4 3.6 3.8 VOH (V) 4.0 4.2 4.4 4.6 VOH > VDD –0.8 V @ IOH = –2.0 mA VOH > VDD –1.5 V @ IOH = –10.0 mA Figure 23-5. Typical High-Side Driver Characteristics – Ports PTB5–PTB0, PTD6–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) 0 IOH (mA) –5 –40 0 25 85 –10 –15 –20 –25 1.3 1.5 1.7 1.9 VOH (V) 2.1 2.3 2.5 VOH > VDD –0.3 V @ IOH = –0.
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Freescale Semiconductor, Inc. Electrical Specifications Output Low-Voltage Characteristics 23.10 Output Low-Voltage Characteristics 35 30 –40 0 25 85 IOL (mA) 25 20 15 10 5 Freescale Semiconductor, Inc... 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VOL (V) VOL < 0.4 V @ IOL = 1.6 mA VOL < 1.5 V @ IOL = 10.0 mA Figure 23-7. Typical Low-Side Driver Characteristics – Port PTA3–PTA0 (VDD = 5.5 Vdc) 14 12 –40 0 25 85 IOL (mA) 10 8 6 4 2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VOL (V) VOL < 0.
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Freescale Semiconductor, Inc. Electrical Specifications 60 IOL (mA) 50 40 –40 0 25 85 30 20 10 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VOL (V) Freescale Semiconductor, Inc... VOL < 1.0 V @ IOL = 15 mA Figure 23-9. Typical Low-Side Driver Characteristics – Port PTC1–PTC0 (VDD = 4.5 Vdc) 30 IOL (mA) 25 –40 0 25 85 20 15 10 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VOL (V) VOL < 0.8 V @ IOL = 10 mA Figure 23-10. Typical Low-Side Driver Characteristics – Port PTC1–PTC0 (VDD = 2.
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Freescale Semiconductor, Inc. Electrical Specifications Output Low-Voltage Characteristics 35 30 –40 0 25 85 IOL (mA) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 1.4 VOL (V) Freescale Semiconductor, Inc... VOL < 0.4 V @ IOL = 1.6 mA VOL < 1.5 V @ IOL = 10.0 mA Figure 23-11. Typical Low-Side Driver Characteristics – Ports PTB5–PTB0, PTD6–PTD0, and PTE1–PTE0 (VDD = 5.5 Vdc) 14 12 –40 0 25 85 IOL (mA) 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VOL (V) VOL < 0.3 V @ IOL = 0.
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Freescale Semiconductor, Inc. Electrical Specifications 23.11 Typical Supply Currents 16 14 12 IDD (mA) 10 8 Freescale Semiconductor, Inc... 6 4 5.5 V 3.6 V 2 0 0 1 2 3 4 5 fbus (MHz) 6 7 8 9 Figure 23-13. Typical Operating IDD, with All Modules Turned On (–40 °C to 125 °C) 5.0 4.5 4.0 IDD (mA) 3.5 3.0 2.5 2.0 1.5 1.0 5.5 V 3.6 V 0.5 0 0 1 2 3 4 fbus (MHz) 5 6 7 8 Figure 23-14.
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Freescale Semiconductor, Inc. Electrical Specifications Typical Supply Currents 1.35 1.30 IDD (µA) 1.25 1.20 1.15 Freescale Semiconductor, Inc... 1.10 5.5 V 3.6 V 1.05 1 0 1 2 3 4 5 fbus (MHz) 6 7 8 9 Figure 23-15. Typical Stop Mode IDD, with all Modules Disabled (–40 °C to 125 °C) MC68HC908GR8 — Rev 4.0 MOTOROLA Technical Data Electrical Specifications For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 23.12 ADC Characteristics Characteristic(1) Symbol Min Max Unit Comments Supply voltage VDDAD 2.7 (VDD min) 5.5 (VDD max) V VDDAD should be tied to the same potential as VDD via separate traces. Input voltages VADIN 0 VDDAD V VADIN <= VREFH Resolution BAD 8 8 Bits Absolute accuracy (VREFL = 0 V, VDDAD = VREFH = 5 V ± 10%) AAD −− ±1 LSB Includes quantization ADC internal clock fADIC 0.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 5.0 V SPI Characteristics 23.13 5.
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Freescale Semiconductor, Inc. Electrical Specifications 23.14 3.0 V SPI Characteristics Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 3.0 V SPI Characteristics SS INPUT SS PIN OF MASTER HELD HIGH 1 SPSCK OUTPUT CPOL = 0 NOTE SPSCK OUTPUT CPOL = 1 NOTE 5 4 5 4 6 MISO INPUT MSB IN BITS 6–1 11 MOSI OUTPUT 7 MASTER MSB OUT LSB IN 10 11 BITS 6–1 MASTER LSB OUT Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
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Freescale Semiconductor, Inc. Electrical Specifications SS INPUT 3 1 SPSCK INPUT CPOL = 0 5 4 2 SPSCK INPUT CPOL = 1 5 4 9 8 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Timer Interface Module Characteristics 23.15 Timer Interface Module Characteristics Table 23-8. Timer Interface Module Characteristics Characteristic Input capture pulse width Symbol Min Max Unit tTIH, tTIL 1 — tcyc 23.16 Clock Generation Module Characteristics 23.16.1 CGM Component Specifications Table 23-9. CGM Component Specifications Characteristic Symbol Min Typ Max Unit fXCLK 30 32.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 23.16.2 CGM Electrical Specifications Description Symbol Min Typ Max Unit VDD 2.7 — 5.5 V T –40 25 125 o Crystal reference frequency fRCLK 30 32.768 100 kHz Range nominal multiplier fNOM — 38.4 — kHz VCO center-of-range frequency(1) fVRS 38.4 k — 40.0 M Hz Medium-voltage VCO center-of-range frequency(2) fVRS 38.4 k — 40.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Memory Characteristics 23.17 Memory Characteristics Characteristic RAM data retention voltage FLASH program bus clock frequency Symbol Min Typ Max Unit VRDR 1.3 — — V — 1 — — MHz 32k — 8.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Electrical Specifications Technical Data 386 MC68HC908GR8 — Rev 4.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 24. Mechanical Specifications 24.1 Contents 24.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.3 32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .388 24.4 28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 24.5 28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Mechanical Specifications 24.3 32-Pin LQFP (Case #873A) –T–,–U–,–Z– 4X A A1 0.20 (0.008) AB T-U Z 32 25 1 B AE V B1 Freescale Semiconductor, Inc... AE P -U- -T- DETAIL Y DETAIL Y 8 17 9 9 V1 NOTES: 1. DIMENSIONS AND TOLERANCING AS PER ANSI Y14.5M, 1982 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS CONSISTENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE 4.
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Freescale Semiconductor, Inc. Mechanical Specifications 28-Pin PDIP (Case #710) 24.4 28-Pin PDIP (Case #710) A B Freescale Semiconductor, Inc... 1 G H L N C K M F J D Seating Plane Dim. Min. Max. A 36.45 37.21 B 13.72 14.22 C 3.94 5.08 D 0.36 0.56 F 1.02 1.52 G Notes 1. All dimensions in mm. 2. Positional tolerance of leads (‘D’) shall be within 0.25 mm at maximum material condition, in relation to seating plane and to each other. 3.
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Freescale Semiconductor, Inc. Mechanical Specifications 24.5 28-Pin SOIC (Case #751F) –A– –B– P 0.25 M B M 14 PL 1 Freescale Semiconductor, Inc... R x 45° G J C 0.25 M T B S Dim. Min. Max. A 17.80 18.05 B 7.40 7.60 C 2.35 2.65 D 0.35 0.49 F 0.41 0.90 G Seating Plane K D 28 PL –T– F A S Notes 1. 2. 3. 4. 5. Dimensions ‘A’ and ‘B’ are datums and ‘T’ is a datum surface. Dimensioning and tolerancing per ANSI Y14.5M, 1982. All dimensions in mm.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Section 25. Ordering Information 25.1 Contents 25.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 25.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 25.4 Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 25.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Ordering Information 25.3 MC Order Numbers Table 25-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Ordering Information Development Tools 25.4 Development Tools Table 25-2.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Ordering Information Technical Data 394 MC68HC908GR8 — Rev 4.0 Ordering Information For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Glossary A — See “accumulator (A).” accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode — A mode of PLL operation during startup before the PLL locks on a frequency. Also see "tracking mode." address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary branch instruction — An instruction that causes the CPU to continue processing at a memory location other than the next sequential address. break module — A module in the M68HC08 Family. The break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint — A number written into the break address registers of the break module.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit — One bit of a register manipulated by software to control the operation of the module. control unit — One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary direct memory access module (DMA) — A M68HC08 Family module that can perform data transfers between any two CPU-addressable locations without CPU intervention. For transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster and more code-efficient than CPU interrupts. DMA — See "direct memory access module (DMA).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary illegal address — An address not within the memory map illegal opcode — A nonexistent opcode. I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts are disabled. index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower byte is called X.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary LVI — See "low voltage inhibit module (LVI)." M68HC08 — A Motorola family of 8-bit MCUs. mark/space — The logic 1/logic 0 convention used in formatting data in serial communication. mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used in integrated circuit fabrication to transfer an image onto silicon.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary object code — The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode — A binary code that instructs the CPU to perform an operation. open-drain — An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand — Data on which an operation is performed.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary prescaler — A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program — A set of computer instructions that cause a computer to perform a desired operation or operations. program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of the next instruction or operand that the CPU will use.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary serial communications interface module (SCI) — A module in the M68HC08 Family that supports asynchronous communication. serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports synchronous communication. set — To change a bit from logic 0 to logic 1; opposite of clear.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary timer interface module (TIM) — A module used to relate events in a system to a point in time. timer — A module used to relate events in a system to a point in time. toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a frequency. Also see "acquisition mode.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC908GR8 Revision History Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 Changes from Rev 3.0 published in February 2002 to Rev 4.0 published in June 2002. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 Changes from Rev 2.0 published in January 2002 to Rev 3.0 published in February 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Revision History Changes from Rev 2.0 published in January 2002 to Rev 3.0 published in February 2002 Section Page (in Rev 3.0) Description of change All references to the ROM MC68HC08GR8 removed. Appendix A removed.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T.