Datasheet

Programmable Timer
MC68HC711D3 Data Sheet, Rev. 2.1
90 Freescale Semiconductor
8.3.3 Timer Input Capture 4/Output Compare 5 Register
Use timer input capture 4/output compare 5 (TI4/O5) as either an input capture register or an output
compare register, depending on the function chosen for the I4/O5 pin. To enable it as an input capture
pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level 1. To use it as an
output compare register, set the I4/O5 bit to a logic level 0. Refer to 8.7 Pulse Accumulator.
Address: $0011 — TIC1 (Low)
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
Address: $0012 — TIC2 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
Address: $0013 — TIC2 (Low)
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
Address: $0014 — TIC3 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Unaffected by reset
Address: $0015 — TIC3 (Low)
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: Unaffected by reset
Address: $001E — TI4/O5 (High)
Bit 15 14 13 12 11 10 9 Bit 8
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset:11111111
Address: $001F — TI4/O5 (Low)
Bit 7654321Bit 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset:11111111
= Unimplemented
Figure 8-5. Timer Input Capture 4/Output
Compare 5 Register (TI4/O5)
= Unimplemented
Figure 8-4. Timer Input Capture Registers (TICx) (Continued)