Datasheet

SCI Error Detection

MC68HC711D3 Data Sheet, Rev. 2.1

Freescale Semiconductor 69

6.6 SCI Error Detection

Three error conditions can occur during generation of SCI system interrupts:

• Serial communications data register (SCDR) overrun

• Received bit noise

•Framing

Three bits (OR, NF, and FE) in the serial communications status register (SCSR) indicate if one of these

error conditions exists. The overrun error (OR) bit is set when the next byte is ready to be transferred from

the receive shift register to the SCDR and the SCDR is already full (RDRF bit is set). When an overrun

error occurs, the data that caused the overrun is lost and the data that was already in SCDR is not

disturbed. The OR is cleared when the SCSR is read (with OR set), followed by a read of the SCDR.

The noise flag (NF) bit is set if there is noise on any of the received bits, including the start and stop bits.

The NF bit is not set until the RDRF flag is set. The NF bit is cleared when the SCSR is read (with FE

equal to 1) followed by a read of the SCDR.

When no stop bit is detected in the received data character, the framing error (FE) bit is set. FE is set at

the same time as the RDRF. If the byte received causes both framing and overrun errors, the processor

only recognizes the overrun error. The framing error flag inhibits further transfer of data into the SCDR

until it is cleared. The FE bit is cleared when the SCSR is read (with FE equal to 1) followed by a read of

the SCDR.

6.7 SCI Registers

This subsection describes the five addressable registers in the SCI.

6.7.1 SCI Data Register

The SCI data register (SCDR) is a parallel register that performs two functions. It is the receive data

buffer and writes access the transmit data buffer. Receive and transmit are double buffered.

Address: $002F

Bit 7654321Bit 0

Read:

R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0

Write:

Reset: Unaffected by reset

Figure 6-3. SCI Data Register (SCDR)