Datasheet

Resets, Interrupts, and Low-Power Modes
MC68HC711D3 Data Sheet, Rev. 2.1
54 Freescale Semiconductor
Figure 4-4. Processing Flow Out of Reset (Sheet 2 of 2)
I BIT IN
CCR SET?
2A
Y
N
ANY I-BIT
INTERRUPT
Y
N
PENDING?
FETCH OPCODE
ILLEGAL
OPCODE?
N
Y
WAI
Y
N
INSTRUCTION?
SWI
INSTRUCTION?
Y
N
RTI
INSTRUCTION?
Y
N
EXECUTE THIS
INSTRUCTION
STACK CPU
REGISTERS
N
Y
INTERRUPT
YET?
SET I BIT
STACK CPU
REGISTERS
SET I BIT
FETCH VECTOR
$FFF8, $FFF9
STACK CPU
REGISTERS
FETCH VECTOR
$FFF6, $FFF7
RESTORE CPU
REGISTERS
FROM STACK
1A
STACK CPU
REGISTERS
RESOLVE INTERRUPT
PRIORITY AND FETCH
VECTOR FOR HIGHEST
PENDING SOURCE
SEE Figure 4-5
SET I BIT
START NEXT
INSTRUCTION
SEQUENCE