Datasheet

Interrupts

MC68HC711D3 Data Sheet, Rev. 2.1

Freescale Semiconductor 51

Figure 4-3. Interrupt Stacking Order

4.3.1 Software Interrupt (SWI)

The SWI is executed the same as any other instruction and takes precedence over interrupts only if the

other interrupts are masked (with I and X bits in the CCR set). SWI execution is similar to that of the

maskable interrupts in that it sets the I bit, stacks the central processor unit (CPU) registers, etc.

NOTE

The SWI instruction cannot be executed as long as another interrupt is

pending. However, once the SWI instruction has begun, no other interrupt

can be honored until the first instruction in the SWI service routine is

completed.

4.3.2 Illegal Opcode Trap

Since not all possible opcodes or opcode sequences are defined, an illegal opcode detection circuit has

been included in the MCU. When an illegal opcode is detected, an interrupt is required to the illegal

opcode vector. The illegal opcode vector should never be left uninitialized.

4.3.3 Real-Time Interrupt (RTI)

The real-time interrupt (RTI) provides a programmable periodic interrupt. This interrupt is maskable by

either the I bit in the CCR or the RTI enable (RTII) bit of the timer interrupt mask register 2 (TMSK2). The

rate is based on the MCU E clock and is software selectable to the E ÷ 2

, E ÷ 2

, or E ÷ 2

See PACTL, TMSK2, and TFLG2 register descriptions in Chapter 8 Programmable Timer for control and

status bit information.

4.3.4 Interrupt Mask Bits in the CCR

Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable interrupts and XIRQ. After

minimum system initialization, software may clear the X bit by a TAP instruction, thus enabling XIRQ

interrupts. Thereafter software cannot set the X bit. So, an XIRQ interrupt is effectively a non-maskable

interrupt. Since the operation of the I bit related interrupt structure has no effect on the X bit, the internal

XIRQ

pin remains effectively non-masked. In the interrupt priority logic, the XIRQ interrupt is a higher

priority than any source that is maskable by the I bit. All I bit related interrupts operate normally with their

own priority relationship.

STACK

SP PCL — SP BEFORE INTERRUPT

SP – 1 PCH

SP – 2 IYL

SP – 3 IYH

SP –

4IXL

SP – 5IXH

SP – 6ACCA

SP – 7ACCB

SP – 8CCR

SP – 9 — SP AFTER INTERRUPT