Datasheet

Resets, Interrupts, and Low-Power Modes
MC68HC711D3 Data Sheet, Rev. 2.1
50 Freescale Semiconductor
Table 4-2 provides a list of the interrupts with a vector location in memory for each, as well as the actual
condition code and control bits that mask each interrupt. Figure 4-3 shows the interrupt stacking order.
Table 4-2. Interrupt and Reset Vector Assignments
Vector
Address
Interrupt Source
CCR
Mask
Local
Mask
$FFC0, $FFC1
↓
$FFD4, $FFD5
Reserved — —
$FFD6, $FFD7
SCI serial system:
• SCI transmit complete
• SCI transmit data register empty
• SCI idle line detect
• SCI receiver overrun
• SCI receive data register full
I bit
TCIE
TIE
ILIE
RIE
RIE
$FFD8, $FFD9 SPI serial transfer complete I bit SPIE
$FFDA, $FFDB Pulse accumulator input edge I bit PAII
$FFDC, $FFDD Pulse accumulator overflow I bit PAOVI
$FFDE, $FFDF Timer overflow I bit TOI
$FFE0, $FFE1 Timer input capture 4/output compare 5 I bit I4/O5I
$FFE2, $FFE3 Timer output compare 4 I bit OC4I
$FFE4, $FFE5 Timer output compare 3 I bit OC3I
$FFE6, $FFE7 Timer output compare 2 I bit OC2I
$FFE8, $FFE9 Timer output compare 1 I bit OC1I
$FFEA, $FFEB Timer input capture 3 I bit IC3I
$FFEC, $FFED Timer input capture 2 I bit IC2I
$FFEE, $FFEF Timer input capture 1 I bit IC1I
$FFF0, $FFF1 Real time interrupt I bit RTII
$FFF2, $FFF3 IRQ
(external pin) I bit None
$FFF4, $FFF5 XIRQ
pin (pseudo non-maskable) X bit None
$FFF6, $FFF7 Software interrupt None None
$FFF8, $FFF9 Illegal opcode trap None None
$FFFA, $FFFB COP failure (reset) None NOCOP
$FFFC, $FFFD Clock monitor fail (reset) None CME
$FFFE, $FFFF RESET
None None