Datasheet

Central Processor Unit (CPU)
MC68HC711D3 Data Sheet, Rev. 2.1
44 Freescale Semiconductor
LSRD Logical Shift
Right Double
INH 04 — 3 — — — — 0 ∆∆∆
MUL Multiply 8 by 8 A ∗ B ⇒ D INH 3D — 10 ——————— ∆
NEG (opr) Two’s
Complement
Memory Byte
0 – M ⇒ MEXT
IND,X
IND,Y
70
60
18 60
hh ll
ff
ff
6
6
7
———— ∆∆∆∆
NEGA Two’s
Complement
A
0 – A ⇒ AAINH 40 — 2————∆∆∆∆
NEGB Two’s
Complement
B
0 – B ⇒ BBINH 50 — 2————∆∆∆∆
NOP No operation No Operation INH 01 — 2 — — — — — — — —
ORAA (opr) OR
Accumulator
A (Inclusive)
A + M ⇒ A A IMM
ADIR
AEXT
AIND,X
AIND,Y
8A
9A
BA
AA
18 AA
ii
dd
hh ll
ff
ff
2
3
4
4
5
———— ∆∆0—
ORAB (opr) OR
Accumulator
B (Inclusive)
B + M ⇒ B B IMM
BDIR
BEXT
BIND,X
BIND,Y
CA
DA
FA
EA
18 EA
ii
dd
hh ll
ff
ff
2
3
4
4
5
———— ∆∆0—
PSHA Push A onto
Stack
A ⇒
Stk,SP = SP – 1 A INH 36 — 3 — — — — — — — —
PSHB Push B onto
Stack
B ⇒ Stk,SP = SP – 1 B INH 37 — 3 — — — — — — — —
PSHX Push X onto
Stack (Lo
First)
IX ⇒ Stk,SP = SP – 2 INH 3C — 4 ————————
PSHY Push Y onto
Stack (Lo
First)
IY ⇒ Stk,SP = SP – 2 INH 18 3C — 5 ————————
PULA Pull A from
Stack
SP = SP + 1, A ⇐ StkA INH 32 — 4 ————————
PULB Pull B from
Stack
SP = SP + 1, B ⇐ StkB INH 33 — 4 ————————
PULX Pull X From
Stack (Hi
First)
SP = SP + 2, IX ⇐ Stk INH 38 — 5 ————————
PULY Pull Y from
Stack (Hi
First)
SP = SP + 2, IY ⇐ Stk INH 18 38 — 6 ————————
ROL (opr) Rotate Left EXT
IND,X
IND,Y
79
69
18 69
hh ll
ff
ff
6
6
7
———— ∆∆∆∆
ROLA Rotate Left A A INH 49 — 2 — — — — ∆∆∆∆
ROLB Rotate Left B B INH 59 — 2 — — — — ∆∆∆∆
ROR (opr) Rotate Right EXT
IND,X
IND,Y
76
66
18 66
hh ll
ff
ff
6
6
7
———— ∆∆∆∆
RORA Rotate Right A A INH 46 — 2 — — — — ∆∆∆∆
RORB Rotate Right B B INH 56 — 2 — — — — ∆∆∆∆
RTI Return from
Interrupt
See Figure 3-2 INH 3B — 12 ∆↓∆∆∆∆∆∆
Table 3-2. Instruction Set (Sheet 6 of 8)
Mnemonic Operation Description
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
C
0
b7 b0A
B
b7
b0
C
b7 b0
C
b7 b0
C
b7 b0
C
b7 b0
C
b7 b0
C
b7
b0