Datasheet

Central Processor Unit (CPU)
MC68HC711D3 Data Sheet, Rev. 2.1
42 Freescale Semiconductor
COMA Ones
Complement
A
$FF – A ⇒ AA INH 43 — 2 ————∆∆01
COMB Ones
Complement
B
$FF – B ⇒ BB INH 53 — 2 ————∆∆01
CPD (opr) Compare D to
Memory 16-Bit
D – M : M + 1 IMM
DIR
EXT
IND,X
IND,Y
1A 83
1A 93
1A B3
1A A3
CD A3
jj kk
dd
hh ll
ff
ff
5
6
7
7
7
———— ∆∆∆∆
CPX (opr) Compare X to
Memory 16-Bit
IX – M : M + 1 IMM
DIR
EXT
IND,X
IND,Y
8C
9C
BC
AC
CD AC
jj kk
dd
hh ll
ff
ff
4
5
6
6
7
———— ∆∆∆∆
CPY (opr) Compare Y to
Memory 16-Bit
IY – M : M + 1 IMM
DIR
EXT
IND,X
IND,Y
18 8C
18 9C
18 BC
1A AC
18 AC
jj kk
dd
hh ll
ff
ff
5
6
7
7
7
———— ∆∆∆∆
DAA Decimal Adjust
A
Adjust Sum to BCD INH 19 — 2 — — — — ∆∆∆∆
DEC (opr) Decrement
Memory Byte
M – 1 ⇒ MEXT
IND,X
IND,Y
7A
6A
18 6A
hh ll
ff
ff
6
6
7
———— ∆∆∆—
DECA Decrement
Accumulator
A
A – 1 ⇒ AAINH 4A — 2————∆∆∆—
DECB Decrement
Accumulator
B
B – 1 ⇒ BBINH 5A — 2————∆∆∆—
DES Decrement
Stack Pointer
SP – 1 ⇒ SP INH 34 — 3 ————————
DEX Decrement
Index Register
X
IX – 1 ⇒ IX INH 09 — 3 — — — — — ∆ ——
DEY Decrement
Index Register
Y
IY – 1 ⇒ IY INH 18 09 — 4 — — — — — ∆ ——
EORA (opr) Exclusive OR A
with Memory
A ⊕ M ⇒ A A IMM
ADIR
AEXT
AIND,X
AIND,Y
88
98
B8
A8
18 A8
ii
dd
hh ll
ff
ff
2
3
4
4
5
———— ∆∆0—
EORB (opr) Exclusive OR B
with Memory
B ⊕ M ⇒ B B IMM
BDIR
BEXT
BIND,X
BIND,Y
C8
D8
F8
E8
18 E8
ii
dd
hh ll
ff
ff
2
3
4
4
5
———— ∆∆0—
FDIV Fractional
Divide 16 by 16
D / IX ⇒ IX; r ⇒ D INH 03 — 41 ————— ∆∆∆
IDIV Integer Divide
16 by 16
D / IX ⇒
IX; r ⇒ D INH 02 — 41 ————— ∆ 0 ∆
INC (opr) Increment
Memory Byte
M + 1 ⇒ MEXT
IND,X
IND,Y
7C
6C
18 6C
hh ll
ff
ff
6
6
7
———— ∆∆∆—
INCA Increment
Accumulator
A
A + 1 ⇒ A A INH 4C — 2 — — — — ∆∆∆—
INCB Increment
Accumulator
B
B + 1 ⇒ B B INH 5C — 2 — — — — ∆∆∆—
INS Increment
Stack Pointer
SP + 1 ⇒ SP INH 31 — 3 ————————
Table 3-2. Instruction Set (Sheet 4 of 8)
Mnemonic Operation Description
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C