Datasheet

Central Processor Unit (CPU)
MC68HC711D3 Data Sheet, Rev. 2.1
40 Freescale Semiconductor
ADDB (opr) Add Memory to
B
B + M ⇒ BBIMM
BDIR
BEXT
BIND,X
BIND,Y
CB
DB
FB
EB
18 EB
ii
dd
hh ll
ff
ff
2
3
4
4
5
—— ∆ — ∆∆∆∆
ADDD (opr) Add 16-Bit to D D + (M : M + 1) ⇒ DIMM
DIR
EXT
IND,X
IND,Y
C3
D3
F3
E3
18 E3
jj kk
dd
hh ll
ff
ff
4
5
6
6
7
———— ∆∆∆∆
ANDA (opr) AND A with
Memory
A • M ⇒ AA IMM
A DIR
A EXT
AIND,X
AIND,Y
84
94
B4
A4
18 A4
ii
dd
hh ll
ff
ff
2
3
4
4
5
———— ∆∆0—
ANDB (opr) AND B with
Memory
B • M ⇒ BBIMM
BDIR
BEXT
BIND,X
BIND,Y
C4
D4
F4
E4
18 E4
ii
dd
hh ll
ff
ff
2
3
4
4
5
———— ∆∆0—
ASL (opr) Arithmetic Shift
Left
EXT
IND,X
IND,Y
78
68
18 68
hh ll
ff
ff
6
6
7
———— ∆∆∆∆
ASLA Arithmetic Shift
Left A
A INH 48 — 2 ———— ∆∆∆∆
ASLB Arithmetic Shift
Left B
B INH 58 — 2 ———— ∆∆∆∆
ASLD Arithmetic Shift
Left D
INH 05 — 3 — — — — ∆∆∆∆
ASR Arithmetic Shift
Right
EXT
IND,X
IND,Y
77
67
18 67
hh ll
ff
ff
6
6
7
———— ∆∆∆∆
ASRA Arithmetic Shift
Right A
A INH 47 — 2 ———— ∆∆∆∆
ASRB Arithmetic Shift
Right B
B INH 57 — 2 ———— ∆∆∆∆
BCC (rel) Branch if Carry
Clear
? C = 0 REL 24 rr 3 ————————
BCLR (opr)
(msk)
Clear Bit(s) M • (mm
) ⇒ M DIR
IND,X
IND,Y
15
1D
18 1D
dd mm
ff mm
ff mm
6
7
8
———— ∆∆0—
BCS (rel) Branch if Carry
Set
? C = 1 REL 25 rr 3 ————————
BEQ (rel) Branch if = Zero ? Z = 1 REL 27 rr 3 — — — — — — — —
BGE (rel) Branch if ∆ Zero ? N ⊕ V = 0 REL 2C rr 3 ————————
BGT (rel) Branch if > Zero ? Z + (N ⊕ V) = 0 REL 2E rr 3 ————————
BHI (rel) Branch if
Higher
? C + Z = 0 REL 22 rr 3 ————————
BHS (rel) Branch if
Higher or Same
? C = 0 REL 24 rr 3 ————————
BITA (opr) Bit(s) Test A
with Memory
A • M A IMM
ADIR
AEXT
AIND,X
AIND,Y
85
95
B5
A5
18 A5
ii
dd
hh ll
ff
ff
2
3
4
4
5
———— ∆∆0—
Table 3-2. Instruction Set (Sheet 2 of 8)
Mnemonic Operation Description
Addressing Instruction Condition Codes
Mode Opcode Operand Cycles S X H I N Z V C
C
0
b7 b0
C
0
b7 b0
C
0
b7 b0
C
0
b7 b0A
B
b7
b0
C
b7 b0
C
b7 b0
C
b7 b0